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PDF ( 数据手册 , 数据表 ) AD6653

零件编号 AD6653
描述 IF Diversity Receiver
制造商 Analog Devices
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AD6653 数据手册, 描述, 功能
IF Diversity Receiver
AD6653
FEATURES
SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at
70 MHz @ 150 MSPS
SFDR = 83 dBc to 70 MHz @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
Integrated dual-channel ADC
Sample rates up to 150 MSPS
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC)
32-bit, complex, numerically controlled oscillator (NCO)
Decimating half-band filter and FIR filter
Supports real and complex output modes
Fast attack/threshold detect bits
Composite signal monitor
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
PRODUCT HIGHLIGHTS
1. Integrated dual, 12-bit, 125 MSPS/150 MSPS ADC.
2. Integrated wideband decimation filter and 32-bit
complex NCO.
3. Fast overrange detect and signal monitor with serial output.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Flexible output modes, including independent CMOS,
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
6. SYNC input allows synchronization of multiple devices.
7. 3-bit SPI port for register programming and register readback.
AVDD
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VIN+A
VIN–A
SHA
FUNCTIONAL BLOCK DIAGRAM
FD[0:3]A
DVDD
FD BITS/THRESHOLD
DETECT
ADC
I
LP/HP
DECIMATING
HB FILTER +
Q FIR
DRVDD
AD6653
D11A
D0A
VREF
SENSE
CML
RBIAS
REF
SELECT
VIN–B
VIN+B
SHA
SIGNAL
MONITOR
ADC
32-BIT
TUNING
NCO
Q
LP/HP
DECIMATING
HB FILTER +
I FIR
fADC/8
NCO
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
DCO
GENERATION
PROGRAMMING DATA
MULTI-CHIP
SYNC
FD BITS/THRESHOLD SIGNAL MONITOR
DETECT
DATA
SIGNAL MONITOR
INTERFACE
SPI
CLK+
CLK–
DCOA
DCOB
D11B
D0B
AGND SYNC
FD[0:3]B
SMI SMI SMI
SDIO/ SCLK/ CSB
SDFS SCLK/ SDO/
DCS DFS
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
DRGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.







AD6653 pdf, 数据表
AD6653
Parameter
LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD),
ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD),
Reduced Swing Mode
Output Offset Voltage (VOS),
Reduced Swing Mode
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2 Pull down.
AD6653BCPZ-125
Temp Min
Typ Max
Full 1.22
Full 0
Full −90
Full −10
Full
Full
3.6
0.6
−134
+10
26
5
Full 3.29
Full 3.25
Full
Full
Full 1.79
Full 1.75
Full
Full
Full 250
Full 1.15
Full 150
Full 1.15
0.2
0.05
0.2
0.05
350 450
1.25 1.35
200 280
1.25 1.35
AD6653BCPZ-150
Min Typ Max
1.22 3.6
0 0.6
−90 −134
−10 +10
26
5
3.29
3.25
0.2
0.05
1.79
1.75
0.2
0.05
250 350 450
1.15 1.25 1.35
150 200 280
1.15 1.25 1.35
Unit
V
V
μA
μA
pF
V
V
V
V
V
V
V
V
mV
V
mV
V
Rev. 0 | Page 8 of 80







AD6653 equivalent, schematic
AD6653
DRVDD 1
DNC 2
DNC 3
D0– (LSB) 4
D0+ (LSB) 5
D1– 6
D1+ 7
D2– 8
D2+ 9
DCO– 10
DCO+ 11
D3– 12
D3+ 13
D4– 14
D4+ 15
D5– 16
DNC = DO NOT CONNECT
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD6653
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48 SCLK/DFS
47 SDIO/DCS
46 AVDD
45 AVDD
44 VIN+B
43 VIN–B
42 RBIAS
41 CML
40 SENSE
39 VREF
38 VIN–A
37 VIN+A
36 AVDD
35 SMI SDFS
34 SMI SCLK/PDWN
33 SMI SDO/OEB
Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
20, 64
DRGND
Ground
Digital Output Ground.
1, 21 DRVDD
Supply
Digital Output Driver Supply (1.8 V to 3.3 V).
24, 57
DVDD
Supply
Digital Power Supply (1.8 V Nominal).
36, 45, 46
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
0
AGND
Ground
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
2, 3, 62, 63
DNC
Do Not Connect.
ADC Analog
37
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
38 VIN−A
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Input
Input
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
43
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
39 VREF
Input/Output Voltage Reference Input/Output.
40
SENSE
Input
Voltage Reference Mode Select. See Table 11 for details.
42 RBIAS
Input/Output External Reference Bias Resistor.
41 CML
Output
Common-Mode Level Bias Output for Analog Inputs.
49 CLK+
Input
ADC Clock Input—True.
50 CLK−
Input
ADC Clock Input—Complement.
ADC Fast Detect Outputs
54 FD0+
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details.
53 FD0−
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17
for details.
56 FD1+
Output
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details.
55 FD1−
Output
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17
for details.
59 FD2+
Output
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details.
58 FD2−
Output
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17
for details.
61 FD3+
Output
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details.
60 FD3−
Output
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17
for details.
Rev. 0 | Page 16 of 80










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