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PDF ( 数据手册 , 数据表 ) WCMC8016V9X

零件编号 WCMC8016V9X
描述 8Mb (512K x 16) Pseudo Static RAM
制造商 Weida Semiconductor
LOGO Weida Semiconductor LOGO 


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WCMC8016V9X 数据手册, 描述, 功能
ADVANCE INFORMATION
WCMC8016V9X
8Mb (512K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access Time: 70ns
• Ultra-low active power
— Typical active current: 2.0mA @ f = 1 MHz
— Typical active current: 11mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, CE2, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48 Ball BGA Package
Functional Description[1]
The WCMC8016V9X is a high-performance CMOS pseudo
static RAM organized as 512K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life® (MoBL®) in
portable applications such as cellular telephones. The device
can be put into standby mode reducing power consumption by
more than 99% when deselected using CE LOW, CE2 HIGH
or both BHE and BLE are HIGH. The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH, CE2 LOW OE is deasserted HIGH), or
during a write operation (Chip Enabled and Write Enable WE
LOW). The device also has an automatic power-down feature
that significantly reduces power consumption by 99% when
addresses are not toggling even when the chip is selected
(Chip Enable CE LOW, CE2 HIGH and both BHE and BLE are
LOW). Reading from the device is accomplished by asserting
the Chip Enables (CE LOW and CE2 HIGH) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the Truth Table for a
complete description of read and write modes
Logic Block Diagram
DATA IN DRIVERS
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A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
512K x 16
RAM Array
1T
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
BHE
WE
OE
BLE
CE2
CE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress .com.
WeidaSemiconductor, Inc.
38-14026
Revised August 2003







WCMC8016V9X pdf, 数据表
ADVANCE INFORMATION
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) [13, 14,16, 17, 18]
ADDRESS
CE
t
WC
tSCE
CE2
WE
tA W
tSA tPWE
BHE/BLE
tBW
WCMC8016V9X
tH A
OE
DATAI/O DON’T CARE
Write Cycle 2 (CE or CE2 Controlled)[13, 14,16, 17, 18]
ADDRESS
CE
tSD
VALID DATA
tWC
tSCE
CE2
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WE
tSA
tA W
tPWE
BHE /BLE
t
BW
tHD
tH A
OE
DATA I/O
DON’T CARE
tSD
VALID DATA
tHD
tH Z O E
Notes:
16. Data I/O is high impedance if OE = VIH .
17. If Chip Enable goes INACTIVE and CE2 goes LOW simultaneously with WE = V IH, the output remains in a high-impedance state.
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
38-14026
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