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PDF ( 数据手册 , 数据表 ) CG6257AM

零件编号 CG6257AM
描述 4Mb (256K x 16) Pseudo Static RAM
制造商 Weida Semiconductor
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CG6257AM 数据手册, 描述, 功能
PRELIMINARY
CG6257AM
4Mb (256K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access Time: 70ns
• Ultra-low active power
— Typical active current: 2.0mA @ f = 1 MHz
— Typical active current: 13mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48 Ball BGA Package
Functional Description[1]
The CG6257AM is a high-performance CMOS Pseudo static
RAM organized as 256K words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life® (MoBL) in
portable applications such as cellular telephones. The device
can be put into standby mode reducing power consumption by
more than 99% The device can also be put into standby mode
when deselected (CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE HIGH ), outputs
are disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW). The addresses must not
be toggled once the read is started on the device.
Writing to the device is accomplished by taking Chip Enables
(CE LOW ) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enables (CE LOW) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. See the truth table at the back of this datasheet for a
complete description of read and write modes
Logic Block Diagram
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A10
A9
A
A
8
7
A6
A5
A4
A3
A2
A
A
1
0
DATA IN DRIVERS
256K × 16
RAM Array
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
Power- Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE
CE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Weida Semiconductor, Inc.
38-XXXXX
Revised August 2003







CG6257AM pdf, 数据表
PRELIMINARY
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) [13, 14, 17, 18, 19]
ADDRESS
CE
WE
BHE/BLE
t WC
tSCE
tAW
tSA tPWE
tBW
CG6257AM
tHA
OE
DATAI/O DON’T CARE
tHZOE
Write Cycle 2 (CE Controlled)[13, 14, 17, 18, 19]
tSD
VALID DATA
ADDRESS
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WE
BHE/BLE
t WC
tSA tAW
tSCE
tPWE
tBW
tHD
tHA
OE
DATA I/O
DON’T CARE
tSD
VALID DATA
tHD
tHZOE
Notes:
17. Data I/O is high impedance if OE = VIH.
18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state.
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
38-XXXXX
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