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PDF ( 数据手册 , 数据表 ) 93AA56A

零件编号 93AA56A
描述 (93AAxxx) 1K-16K Microwire Compatible Serial EEPROMs
制造商 Microchip Technology
LOGO Microchip Technology LOGO 


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93AA56A 数据手册, 描述, 功能
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1K-16K Microwire Compatible Serial EEPROMs
Features:
• Densities from 1 Kbits through 16 Kbits
• Low-power CMOS technology
• Available with or without ORG function:
With ORG function:
- ORG pin at Logic Low: 8-bit word
- ORG pin at Logic High: 16-bit word
Without ORG function:
- ‘A’ version: 8-bit word
- ‘B’ version: 16-bit word
• Program Enable pin:
- Write-protect for entire array
(93XX76C and 93XX86C only)
• Self-timed Erase/Write cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential Read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Pb-free and RoHS compliant
• Temperature ranges supported:
www.DataSheet4U.com
- Industrial (I)
-40°C to +85°C
- Automotive (E)
-40°C to +125°C
Pin Function Table
Name
Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
PE Program Enable
ORG Memory Configuration
VCC
Note:
Power Supply
ORG and PE functionality not available in
all products. See Table 1-1, Device
Selection Table.
Description:
Microchip Technology Inc. supports the 3-wire
Microwire bus with low-voltage serial Electrically
Erasable PROMs (EEPROM) that range in density
from 1 Kbits up to 16 Kbits. Each density is available
with and without the ORG functionality, and selected
by the part number ordered. Advanced CMOS technol-
ogy makes these devices ideal for low-power, nonvol-
atile memory applications. The entire series of
Microwire devices are available in the standard 8-lead
PDIP and SOIC packages, as well as the more
advanced packaging such as the 8-lead MSOP, 8-lead
TSSOP, 6-lead SOT-23, and 8-lead DFN (2x3). All
packages are Pb-free.
Pin Diagrams (not to scale)
PDIP/SOIC
(P, SN)
CS 1
CLK 2
DI 3
DO 4
8
7
6
5
ROTATED SOIC
(ex: 93LC46BX)
VCC
NC
(2,3)
PE VCC
(1,3)
ORG CS
1
2
3
(1,3)
8 ORG
7 VSS
6 DO
VSS CLK 4
5 DI
DFN (MC)
CS 1
CLK 2
DI 3
DO 4
8 VCC
7 PE(2,3)
6 ORG(1,3)
5 VSS
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
8 VCC
DO
7 PE(2,3)
6 ORG(1,3) VSS
5 VSS
DI
SOT-23
(OT)
16
25
34
VCC
CS
CLK
Note 1: ORG pin: Only on 93XX46C/56C/66C/76C/86C.
2: PE pin: Only on 93XX76C/86C.
3: ORG/PE: No internal connections on 93XXA/B.
© 2007 Microchip Technology Inc.
DS21929D-page 1







93AA56A pdf, 数据表
93XX46X/56X/66X/76X/86X
TABLE 2-5: INSTRUCTION SET FOR 93XX66A/B/C
Instruction SB Opcode
Address
Data In
Data Out
Req.
CLK
Cycles
93XX66B OR 93XX66C WITH ORG = 1 (16-BIT WORD ORGANIZATION)
ERASE
1 11
A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
ERAL
1 00
10xxxxxx
— (RDY/BSY)
EWDS
1 00
00xxxxxx
High-Z
EWEN
1 00
11xxxxxx
High-Z
READ
1 10
A7 A6 A5 A4 A3 A2 A1 A0 —
D15-D0
WRITE
1 01
A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY)
WRAL
1 00
0 1 x x x x x x D15-D0 (RDY/BSY)
93XX66A OR 93XX66C WITH ORG = 0 (8-BIT WORD ORGANIZATION)
ERASE
1 11
A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
ERAL
1 00
10xxxxxxx
— (RDY/BSY)
EWDS
1 00
00xxxxxxx
High-Z
EWEN
1 00
11xxxxxxx
High-Z
READ
1 10
A8 A7 A6 A5 A4 A3 A2 A1 A0 —
D7-D0
WRITE
1 01
A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/BSY)
WRAL
1 00
0 1 x x x x x x x D7-D0 (RDY/BSY)
11
11
11
11
27
27
27
12
12
12
12
20
20
20
TABLE 2-6: INSTRUCTION SET FOR 93XX76A/B/C
Instruction SB Opcode
Address
Data In
Data Out
Req.
CLK
Cycles
93XX76B OR 93XX76C WITH ORG = 1 (16-BIT WORD ORGANIZATION)
ERASE
1 11
www.DataSheet4U.com
ERAL
1 00
x A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
10x x x x x x x x
— (RDY/BSY)
EWDS
1 00
00x x x x x x x x
High-Z
EWEN
1 00
11x x x x x x x x
High-Z
READ
1 10
x A8 A7 A6 A5 A4 A3 A2 A1 A0 —
D15-D0
WRITE
1 01
x A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY)
WRAL
1 00
0 1 x x x x x x x x D15-D0 (RDY/BSY)
93XX76A OR 93XX76C WITH ORG = 0 (8-BIT WORD ORGANIZATION)
ERASE
1 11 x A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
ERAL
1
00
1 0xxxxxxxxx
— (RDY/BSY)
EWDS
1
00
0 0xxxxxxxxx
High-Z
EWEN
1
00
1 1xxxxxxxxx
High-Z
READ
1 10 x A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 —
D7-D0
WRITE
1 01 x A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/BSY)
WRAL
1 00 0 1 x x x x x x x x x D7-D0 (RDY/BSY)
13
13
13
13
29
29
29
14
14
14
14
22
22
22
DS21929D-page 8
© 2007 Microchip Technology Inc.







93AA56A equivalent, schematic
93XX46X/56X/66X/76X/86X
3.9 WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AAXX and 93LCXX devices, after the last data
bit is clocked into DI, the falling edge of CS initiates the
self-timed auto-erase and programming cycle. For
93CXX devices, the self-timed auto-erase and pro-
gramming cycle is initiated by the rising edge of CLK on
the last data bit. Clocking of the CLK pin is not neces-
sary after the device has entered the WRAL cycle. The
WRAL command does include an automatic ERAL
cycle for the device. Therefore, the WRAL instruction
does not require an ERAL instruction, but the chip must
be in the EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be 4.5V for proper operation of WRAL.
Note:
For devices with PE functionality such as
the 93XX76C or 93XX86C, the write
sequence requires a logic high signal on
the PE pin prior to the rising edge of clock
on the last data bit.
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
FIGURE 3-10:
CS
WRAL TIMING FOR 93AAXX AND 93LCXX DEVICES
TCSL
CLK
DI 1 0 0 0 1 X ••• x Dx ••• D0
DO High-Z
www.DataShVeCetC4Um.cuosmt be 4.5V for proper operation of WRAL.
TSV TCZ
Busy
Ready
HIGH-Z
TWL
FIGURE 3-11:
WRAL TIMING FOR 93CXX DEVICES
CS
TCSL
CLK
DI 1 0 0 0 1 X ••• x Dx ••• D0
TSV TCZ
DO High-Z
Busy Ready HIGH-Z
TWL
DS21929D-page 16
© 2007 Microchip Technology Inc.










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