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PDF ( 数据手册 , 数据表 ) AD9122

零件编号 AD9122
描述 Digital-to-Analog Converter
制造商 Analog Devices
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AD9122 数据手册, 描述, 功能
Dual, 16-Bit, 1230 MSPS,
TxDAC+ Digital-to-Analog Converter
AD9122
FEATURES
Flexible LVDS interface allows word, byte, or nibble load
Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Integrated 2×/4×/8× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain, dc offset, and phase adjustment for sideband
suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS,
full operating conditions
72-lead, exposed paddle LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9122 is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a sample rate of 1230 MSPS,
permitting multicarrier generation up to the Nyquist frequency.
The AD9122 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod-
ulation, and gain and offset compensation. The DAC outputs
are optimized to interface seamlessly with analog quadrature
modulators, such as the ADL537x F-MOD series from Analog
Devices, Inc. A 4-wire serial port interface provides for program-
ming/readback of many internal parameters. Full-scale output
current can be programmed over a range of 8.7 mA to 31.7 mA.
The AD9122 comes in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies (IF).
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. Current outputs are easily configured for various single-
ended or differential circuit topologies.
4. Flexible LVDS digital interface allows the standard 32-wire
bus to be reduced to one-half or one-quarter of the width.
COMPANION PRODUCTS
IQ Modulators: ADL5370, ADL537x family
IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family
Clock Drivers: AD9516, AD951x family
Voltage Regulator Design Tool: ADIsimPower
Additional companion products on the AD9122 product page
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC fIF
DIGITAL
BASEBAND
PROCESSOR
2
SIN
COS
2
2/4 I DAC
2/4 Q DAC
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
LO – fIF
ANTIALIASING
FILTER
AQM PA
LO
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.







AD9122 pdf, 数据表
AD9122
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
AVDD33 to AVSS, EPAD, CVSS, DVSS
IOVDD to AVSS, EPAD, CVSS, DVSS
DVDD18, CVDD18 to AVSS, EPAD,
CVSS, DVSS
AVSS to EPAD, CVSS, DVSS
EPAD to AVSS, CVSS, DVSS
CVSS to AVSS, EPAD, DVSS
DVSS to AVSS, EPAD, CVSS
FSADJ, REFIO, IOUT1P, IOUT1N,
IOUT2P, IOUT2N to AVSS
D[15:0]P, D[15:0]N, FRAMEP, FRAMEN,
DCIP, DCIN to EPAD, DVSS
DACCLKP, DACCLKN, REFCLKP,
REFCLKN to CVSS
RESET, IRQ, CS, SCLK, SDIO, SDO
to EPAD, DVSS
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +2.1 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD33 + 0.3 V
−0.3 V to DVDD18 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
−0.3 V to IOVDD + 0.3 V
125°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed pad (EPAD) of the 72-lead LFCSP must be
soldered to the ground plane (AVSS). The EPAD provides an
electrical, thermal, and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer board in
still air. Airflow increases heat dissipation, effectively reducing
θJA and θJB.
Table 7. Thermal Resistance
Package
θJA θJB
72-Lead LFCSP 20.7 10.9
θJC
1.1
Unit Conditions
°C/W EPAD soldered
to ground plane
ESD CAUTION
Rev. B | Page 8 of 60







AD9122 equivalent, schematic
AD9122
START 133.06MHz
#RES BW 30kHz
VBW 30kHz
STOP 166.94MHz
SWEEP 143.6ms (601 PTS)
RMS RESULTS
CARRIER POWER
–10.00dBm/
3.840MHz
FREQ
OFFSET REF BW
5.00MHz 3.840MHz
10.00MHz 3.840MHz
15.00MHz 2.888MHz
LOWER
dBc dBm
–75.96 –85.96
–85.33 –95.33
–95.81 –95.81
UPPER
dBc dBm
–77.13 –87.13
–85.24 –95.25
–85.43 –95.43
Figure 34. One-Carrier W-CDMA ACLR Performance, IF = ~150 MHz
START 125.88MHz
#RES BW 30kHz
VBW 30kHz
STOP 174.42MHz
SWEEP 206.9ms (601 PTS)
TOTAL CARRIER POWER –11.19dBm/15.3600MHz
RRC FILTER: OFF FILTER ALPHA 0.22
REF CARRIER POWER –16.89dBm/3.84000MHz
1 –16.92dBm
2 –16.89dBm
3 –17.43dBm
4 –17.64dBm
OFFSET FREQ
5.000MHz
10.00MHz
15.00MHz
INTEG BW
3.840MHz
3.840MHz
3.840MHz
LOWER
dBc dBm
–65.88 –82.76
–68.17 –85.05
–70.42 –87.31
UPPER
dBc dBm
–67.52 –84.40
–69.91 –86.79
–71.40 –88.28
Figure 35. Four-Carrier W-CDMA ACLR Performance, IF = ~150 MHz
Rev. B | Page 16 of 60










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