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PDF ( 数据手册 , 数据表 ) C8051F316

零件编号 C8051F316
描述 (C8051F310 - C8051F317) 8/16 kB ISP Flash MCU Family
制造商 Silicon Laboratories
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C8051F316 数据手册, 描述, 功能
C8051F310/1/2/3/4/5/6/7
8/16 kB ISP Flash MCU Family
Analog Peripherals
- 10-Bit ADC (C8051F310/1/2/3/6 only)
Up to 200 ksps
Up to 21, 17, or 13 external single-ended or differen-
tial inputs
VREF from external pin or VDD
Built-in temperature sensor
External conversion start input
- Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
(Comparator0)
Low current (< 0.5 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug
(no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-Chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 5 mA at 25 MHz;
11 µA at 32 kHz
- Typical stop mode current: 0.1 µA
- Temperature range:
–40 to +85 °C
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 1280 bytes internal data RAM (1024 + 256)
- 16 kB (C8051F310/1/6/7) or 8 kB (C8051F312/3/4/5)
Flash; In-system programmable in 512-byte sectors
Digital Peripherals
- 29/25/21 Port I/O;
All 5 V tolerant with high sink current
- Hardware enhanced UART, SMBus™, and SPI™
serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five
capture/compare modules
- Real time clock capability using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
- 32-pin LQFP (C8051F310/2/4)
- 28-pin QFN (C8051F311/3/5)
- 24-pin QFN (C8051F316/7)
ANALOG
PERIPHERALS
A
M
U
X
10-bit
200ksps
ADC
+
-
+
TEMP
SENSOR
C8051F310/1/2/3/6 only
-
VOLTAGE
COMPARATORS
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
Port 1
Port 2
Port 3
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB/8 kB
ISP FLASH
14
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
1280 B
SRAM
POR WDT
Rev. 1.7 8/06
Copyright © 2006 by Silicon Laboratories
C8051F31x







C8051F316 pdf, 数据表
C8051F310/1/2/3/4/5/6/7
7. Comparators
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 69
Figure 7.2. Comparator1 Functional Block Diagram ................................................ 70
Figure 7.3. Comparator Hysteresis Plot ................................................................... 71
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 79
Figure 8.2. Memory Map .......................................................................................... 85
9. Reset Sources
Figure 9.1. Reset Sources...................................................................................... 105
Figure 9.2. Power-On and VDD Monitor Reset Timing ........................................... 106
10. Flash Memory
Figure 10.1. Flash Program Memory Map.............................................................. 113
11. External RAM
12. Oscillators
Figure 12.1. Oscillator Diagram.............................................................................. 121
Figure 12.2. 32.768 kHz External Crystal Example................................................ 126
13. Port Input/Output
Figure 13.1. Port I/O Functional Block Diagram ..................................................... 129
Figure 13.2. Port I/O Cell Block Diagram ............................................................... 130
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped ............................... 131
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 132
14. SMBus
Figure 14.1. SMBus Block Diagram ....................................................................... 145
Figure 14.2. Typical SMBus Configuration ............................................................. 146
Figure 14.3. SMBus Transaction ............................................................................ 147
Figure 14.4. Typical SMBus SCL Generation......................................................... 151
Figure 14.5. Typical Master Transmitter Sequence................................................ 157
Figure 14.6. Typical Master Receiver Sequence.................................................... 158
Figure 14.7. Typical Slave Receiver Sequence...................................................... 159
Figure 14.8. Typical Slave Transmitter Sequence.................................................. 160
15. UART0
Figure 15.1. UART0 Block Diagram ....................................................................... 163
Figure 15.2. UART0 Baud Rate Logic .................................................................... 164
Figure 15.3. UART Interconnect Diagram .............................................................. 165
Figure 15.4. 8-Bit UART Timing Diagram............................................................... 165
Figure 15.5. 9-Bit UART Timing Diagram............................................................... 166
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 167
16. Enhanced Serial Peripheral Interface (SPI0)
Figure 16.1. SPI Block Diagram ............................................................................. 173
Figure 16.2. Multiple-Master Mode Connection Diagram ....................................... 176
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 176
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 176
Figure 16.5. Master Mode Data/Clock Timing ........................................................ 178
Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 179
Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 179
8 Rev. 1.7







C8051F316 equivalent, schematic
C8051F310/1/2/3/4/5/6/7
NOTES:
16 Rev. 1.7










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