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PDF ( 数据手册 , 数据表 ) FIN210AC

零件编号 FIN210AC
描述 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
制造商 Fairchild Semiconductor
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FIN210AC 数据手册, 描述, 功能
June 2009
FIN210AC
10-Bit Serializer / Deserializer Supporting Cameras and
Small Displays up to 48MHz
Features
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Selectable Edge Rates
Standby Current
Core Voltage (VDDA/S)
I/O Voltage (VDDP)
ESD (I/O to GND)
Package
Ordering Information
10-bit
48MHz
Camera or LCD
Microcontroller, RGB, YUV
m68 & i86
Yes
<10µA
2.8 to 3.6V
1.65 to 3.6V
15kV
32-Terminal MLP (Preliminary)
42-Ball USS-BGA
FIN210ACMLX (Preliminary)
FIN210ACGFX
Description
The FIN210AC µSerDes™ is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 10-bit data path to four
wires. For camera applications, an additional master clock
can be passed in the opposite direction of data flow. The
device utilizes Fairchild’s proprietary ultra-low power, low-
EMI technology.
Applications
ƒ Slider, Folder, & Clamshell Mobile Handsets
ƒ Printers
ƒ Security Cameras
Typical Application
www.DataSheet4U.com
Baseband
Related Resources
ƒ For samples and questions, please contact:
FIN210AC
Internal
Termination
Built-in voltage
translation
FIN210AC
Camera
Module
+ 2+
-
-
2
++
--
CTL™
Isolates interface
for signal integrity
Camera
Module
Up to 48MHz
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
Figure 1. Mobile Phone Example
www.fairchildsemi.com







FIN210AC pdf, 数据表
Application Diagrams (Continued)
Baseban d
Processor
MASTER CLK
PIXEL CLK
YUV[7:0]
HSYNC
VSYNC
/RES
FIN210AC
Dese rializer
VDDP1
VDD
FIN210AC
Serializer
VDDP2
D3 E4 F4
E4 F4
D3
VDDP VDDS/A
VDDS/A VDDP
A6 CKREF
B5
C1
STROBE
CKP
CKSO+ C5
CKSO- C6
E5 CKSI+
E6 CKSI-
CKP
CKREF
STROBE
C1
A6
B5
B3:E1
E2
F1
DP[8:1]
DP[9]
DP[10]
A4 /ENZ
F6 DIRI
G3 PWS1
G4
A3
G5
PWS0
XTRM
G6 S1
S0
GND
DSI+
DSI-
CKSI-
CKSI+
/DIRO
D5
D6
E6
E5
B6
NC
D6
D5
C6
C5
B6
NC
DSO+
DSO-
CKSO-
CKSO+
/DIRO
DP[8:1]
DP[9]
DP[10]
DIRI
PLL1
PLL0
CTL_ADJ
S1
GND
S0
B3:E1
E2
F1
VDDP2
F6
G3
G4
A4
G5
G6
MASTER CLK
PIXEL CLK
YUV[7:0]
HSYNC
VSYNC
/RES
Figure 6. 8-Bit YUV 1.3MPixel CMOS Imager In Clock Pass-Through Mode
Serializer Configuration:
18MHz to 48MHz Frequency Range (S1=0, S0=1)
Normal Mode (PLL1=0; PLL0=1)
Master clock bypass mode.
Deserializer Configuration:
~2 – 3ns output edge rates (S1=0, S0=1)
~50% CKP PW,(PWS1=PWS0=0)
Baseband
Processor
SYS CLK
/WE
www.DataSheet4UD.actoam[7:0]
A0
/CS0
/RES
A6
B5
NC C1
B3:E1
E2
F1
FIN210AC
Serializer
VDDP1
D3 E4 F4
VDDP VDDS/A
VDD
CKREF
STROBE
CKP
CKSO+ C5
CKSO- C6
E5
E6
DP[8:1]
DP[9]
DP[10]
DSO+
DSO-
D6
D5
D5
D6
FIN210AC
Deserializer
VDDP2
E4 F4
D3
VDDS/A VDDP
CKSI+
CKSI-
CKP C1
CKREF
STROBE
A6
B5
DSI+
DSI-
DP[8:1]
DP[9]
DP[10]
B3:E1
E2
F1
VDDP1F6
G3
G4
DIRI
PLL1
A4 PLL0
G5 CTL_ADJ
G6 S1
S0 GND
CKSI-
CKSI+
EE65NNCC
/DIRO B6NC
NCC6
NCC5
CKSO-
CKSO+
NCB6 /DIRO
GND
/ENZ A4
XTRM A3
DIRI
PWS1
PWS0
F6
G3
G4
S1
G5
G6
S0
Camera Module
MAIN LCD
/WE
DATA[7:0]
A0
/CS
/RES
Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package)
Serializer Configuration:
18MHz to 48MHz Frequency Range (S1=0, S0=1)
CKREF is twice as fast STROBE (PLL1=1; PLL0=0)
CKREF=26MHz & STROBE Frequency=10 MHz
Deserializer Configuration:
~7 – 8ns output edge rates (S1=1, S0=0)
~50% CKP PW,(PWS1=PWS0=0)
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
8
www.fairchildsemi.com







FIN210AC equivalent, schematic
Physical Dimensions (Continued)
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Figure 10. 42-Ball, Ball Grid Array (BGA) Package
Note: Click here for tape and reel specifications, available at:
http://www.fairchildsemi.com/products/analog/pdf/bga42_tr.pdf
Order Number
FIN210ACGFX
Operating
Temperature Range
-30 to 70°C
Package Description
42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch
Eco
Status
RoHS
Packing
Method
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
16
www.fairchildsemi.com










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Fairchild Semiconductor

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