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PDF ( 数据手册 , 数据表 ) WV3HG264M64EEU-D6

零件编号 WV3HG264M64EEU-D6
描述 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED
制造商 White Electronic Designs
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WV3HG264M64EEU-D6 数据手册, 描述, 功能
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED*
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 MT/s DDR2
SDRAM components
VCC = VCCQ = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual Rank
RoHS compliant
Package option
• 240 Pin DIMM
• PCB – 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
December 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com







WV3HG264M64EEU-D6 pdf, 数据表
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED
AC TIMING PARAMETERS (cont'd)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
PARAMETER
SYMBOL
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tIS
tIH
tCCD
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tRPA
tMRD
tDELAY
REFRESH to REFRESH command interval
tRFC
806 665 534 403
MIN MAX MIN MAX MIN MAX MIN MAX UNIT
TBD TBD
200
250
250 ps
TBD TBD
275
375
475 ps
TBD TBD
2
2
2 tCK
TBD TBD
55
55
55 ns
TBD TBD
7.5
7.5
7.5 ns
TBD TBD
15
15
15 ns
TBD TBD 37.5 37.5 37.5 37.5 37.5 37.5
TBD TBD
45 70,000 45 70,000 45 70,000 ns
TBD TBD
7.5
7.5
7.5 ns
TBD TBD
15
15
15 ns
TBD TBD tWR + tRP
tWR + tRP
tWR + tRP
ns
TBD TBD
10
7.5
10 ns
TBD TBD
15
15
15
TBD TBD tWR + tCK
tWR + tCK
tWR + tCK
ns
TBD TBD
2
2
2 tCK
TBD TBD tIS + tCK + tIH
tIS + tCK + tIH
tIS + tCK + tIH
ns
TBD TBD 127.5 127.5 127.5 70,000 127.5 70,000 ns
Average periodic refresh interval
tREFI TBD TBD
7.8
7.8
7.8 µs
Exit self refresh to non-READ command
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
wwwO.DDaTttauSrnh-oenet4U.com
tXSNR
TBD
tRFC (MIN)
TBD + 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
tXSRD TBD TBD
200
200
200 tCK
tISXR TBD TBD
tIS
tIS
tIS ps
tAOND TBD TBD
2
2
2
2
2
2 tCK
tAON
TBD
TBD
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 1000
ps
ODT turn-off delay
ODT turn-off
ODT turn-on (power-down mode)
tAOFD
tAOF
TBD
TBD
tAONPD
TBD
ODT turn-off (power-down mode)
tAOFPD
ODT to power-down entry latency
ODT power-down exit latency
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
A Exit precharge power-down to any non-READ
command.
CKE minimum high/low time
tANPD
tAXPD
tXARD
tXARDS
tXP
tCKE
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD 2.5 2.5 2.5 2.5 2.5 2.5 tCK
TBD
tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600
ps
TBD
tAC (MIN) +
2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN) +
2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN) +
2000
2 x tCK +
tAC (MAX)
+ 1000
ps
TBD
tAC (MIN)
2000
+
2.5
tAC
+
x tCK +
(MAX)
1000
tAC (MIN)
2000
+
2.5
tAC
+
x tCK +
(MAX)
1000
tAC (MIN)
2000
+
2.5
tAC
+
x tCK +
(MAX)
1000
ps
TBD 2 3 3 tCK
TBD 8 8 8 tCK
TBD 2 2 2 tCK
7-AL
TBD
6 - AL
6 - AL
tCK
TBD 2 2 2 tCK
TBD 3 3 3 tCK
NOTE:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
December 2005
Rev. 0
8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com














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