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PDF ( 数据手册 , 数据表 ) WV3HG2256M72AER-D6

零件编号 WV3HG2256M72AER-D6
描述 4GB - 2x256Mx72 DDR2 SDRAM RDIM
制造商 White Electronic Designs
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WV3HG2256M72AER-D6 数据手册, 描述, 功能
White Electronic Designs WV3HG2256M72AER-D6
ADVANCED*
4GB – 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL
FEATURES
240-pin, dual in-line memory module (DIMM)
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
Support ECC error detection and correction
VCC = VCCQ = 1.8V± 0.1V
VCCSPD = +1.7V to +3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh: 64ms 8,192 cycle refresh
Gold edge contacts
RoHS compliant
wwwD.Duaatal SRhaenekt4U.com
Package option
• 240 Pin DIMM
• PCB –30.00mm (1.181") TYP
DESCRIPTION
The WV3HG2256M72AER is a 2x256Mx72 Double Data
Rate DDR2 SDRAM high density module based on 1Gb
DDR2 SDRAM components. This memory module consists
of eighteen stacks of 256Mx4 bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, two - 14 bit
registered buffers in BGA packages mounted on a 240-pin
DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4300
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
April 2006
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com







WV3HG2256M72AER-D6 pdf, 数据表
White Electronic Designs WV3HG2256M72AER-D6
ADVANCED
AC TIMING PARAMETERS (Continued)
VCC = +1.8V ± 0.1V
AC Characteristics
806 665 534 403
Parameter
Symbol Min Max Min Max Min Max Min Max
DQS read preamble
tRPST TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6
DQS write preamble setup time
tWPRES
TBD
TBD
0
0
0
DQS write preamble
tWPRE TBD TBD 0.35 0.35 0.35
DQS write postamble
tWPST TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6
Write command to first DQS latching
transition
tDQSS TBD TBD WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25
Address and control input pulse width
for each input
tIPW
TBD TBD 0.6
0.6
0.6
Address and control input setup time
tISa TBD TBD 200
250
350
Address and control input hold time
tIHa TBD TBD 275
375
475
CAS# to CAS# command delay
tCCD TBD TBD
2
2
2
Active to Active (same bank) command
tRC
TBD TBD 54
55
55
Active bank a to Active b bank
command
tRRD TBD TBD 7.5
7.5
7.5
Active to Read or Write delay
tRCD TBD TBD 15
15
15
Four Bank Activate period
tFAW TBD TBD 37.5 37.5 37.5 37.5 37.5 37.5
Active to precharge command
tRAS TBD TBD 39 70,000 40 70,000 40 70,000
Internal Read to precharge command
delay
tRTP TBD TBD 7.5
7.5
7.5
Write recovery time
tWR TBD TBD 15 15 15
Auto precharge write recovery and
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tDAL TBD TBD tWR+tRP
Interval Write to Read command delay tWTR TBD TBD 7.5
tWR+tRP
7.5
tWR+tRP
10
Precharge command period tRP TBD TBD 15 15 15
Precharge All command period
tRPA TBD TBD tRP+tCK
tRP+tCK
tRP+tCK
Load Mode command cycle time
tMRD TBD TBD
2
2
2
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS+tCK
TBD
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Unit
tCK
ps
tCK
tCK
tCK
tCK
ps
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
Continued on next page
April 2006
Rev. 1
8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com














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