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零件编号 | WV3HG2128M72EEU-D6 | ||
描述 | 2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM | ||
制造商 | White Electronic Designs | ||
LOGO | |||
1 Page
White Electronic Designs WV3HG2128M72EEU-D6
ADVANCED*
2GB – 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM
FEATURES
Unbuffered 240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
VCC = VCCQ = 1.8V
VCCSPD = +1.7V to +3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms/8,192 cycle refresh)
Gold edge contacts
Dual Rank
RoHS compliant
www.DPataaSchkeaegt4eU.ocpomtion
• 240 Pin DIMM
• 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG2128M72EEU is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 128Mx8 bit with 4 banks
DDR2 Synchronous DRAMs in FBGA packages, mounted
on a 240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-6400*
400MHz
6-6-6
OPERATING FREQUENCIES
PC2-5300*
333MHz
5-5-5
PC2-4300
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
August 2006
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs WV3HG2128M72EEU-D6
ADVANCED
AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS
806 665 534
PARAMETER
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
SYMBOL
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tRPA
tMRD
tDELAY
MIN
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
55
7.5
15
37.5
40
7.5
15
tWR+tRP
MAX
37.5
70,000
MIN
55
7.5
15
37.5
40
7.5
15
tWR+tRP
MAX
37.5
70,000
7.5
15
tRP+tCK
2
tIS+tCK
tIH
7.5
15
tRP+tCK
2
tIS+tCK
tIH
REFRESH to Active of Refresh to Refresh
command interfal
tRFC TBD TBD 127.5 70,000 127.5 70,000
Average periodic refresh interval
Exit self refresh to non-READ command
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tREFI
tXSNR
tXSRD
tISXR
tAOND
TBD
TBD
TBD
TBD
TBD
TBD 7.8 7.8
TBD tRFC(MIN)
+10
tRFC(MIN)
+10
TBD 200
200
TBD tIS
tIS
TBD 2 2 2 2
ODT turn-on
tAON
TBD
TBD
tAC(MIN)
tAC(MAX)
+1000
tAC(MIN)
tAC(MAX)
+1000
www.DaOtaDSThteuernt4-oUff.cdoemlay
ODT turn-off
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
ODT to power-down entry latency
ODT power-down exit latency
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
A Exit precharge power-down to any non-
READ command.
CKE minimum high/low time
tAOFD
tAOF
tAONPD
tAOFPD
tANPD
tAXPD
tXARD
tXARDS
tXP
tCKE
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD 2.5 2.5 2.5 2.5
TBD
tAC(MIN)
tAC(MAX)
+600
tAC(MIN)
tAC(MAX)
+600
TBD
tAC(MIN)
+2000
2 x tCK+
tAC(MAX)
+1000
tAC(MIN)
+2000
2 x tCK+
tAC(MAX)
+1000
TBD 2.5 x 2.5 x
tAC(MIN) tCK+ tAC(MIN) tCK+
+2000 tAC(MAX) +2000 tAC(MAX)
+1000
+1000
TBD 3
3
TBD 8
8
TBD 2
2
TBD 7-AL
6-AL
TBD 2
2
TBD 3
3
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
403
MIN MAX
55
7.5
15
37.5 37.5
40 70,000
7.5
15
tWR+tRP
7.5
15
tRP+tCK
2
tIS+tCK
tIH
127.5
70,000
tRFC(MIN)
+10
200
tIS
2
tAC(MIN)
2.5
tAC(MIN)
tAC(MIN)
+2000
tAC(MIN)
+2000
3
8
2
7.8
2
tAC(MAX)
+1000
2.5
tAC(MAX)
+600
2 x tCK+
tAC(MAX)
+1000
2.5 x
tCK+
tAC(MAX)
+1000
6-AL
2
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
µs
ns
tCK
ps
tCK
ps
tCK
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
August 2006
Rev. 1
8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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页数 | 11 页 | ||
下载 | [ WV3HG2128M72EEU-D6.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
WV3HG2128M72EEU-D6 | 2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM | White Electronic Designs |
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