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PDF ( 数据手册 , 数据表 ) LM5027

零件编号 LM5027
描述 Voltage Mode Active Clamp Controller
制造商 National Semiconductor
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LM5027 数据手册, 描述, 功能
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LM5027
August 18, 2009
Voltage Mode Active Clamp Controller
General Description
The LM5027 pulse-width modulation (PWM) controller con-
tains all of the features necessary to implement power con-
verters utilizing the Active Clamp / Reset technique. With the
active clamp technique, higher efficiencies and greater power
densities can be realized compared to conventional catch
winding or RDC clamp / reset techniques. Three control out-
puts are provided: the main power switch control (OUTA), the
active clamp switch control (OUTB), and secondary side syn-
chronous rectifier control (OUTSR). The timing between the
control outputs is adjustable with external resistors that pro-
gram internal precision timers. This controller is designed for
high-speed operation including an oscillator frequency range
up to 1 MHz and total PWM propagation delays less than 50
ns. The LM5027 includes a high-voltage startup regulator with
a maximum input voltage rating of 105V. Additional features
include Line Under Voltage Lockout (UVLO), separate soft-
start of main and synchronous rectifier outputs, a timer for
hiccup mode current limiting, a precision reference, and ther-
mal shutdown.
Features
Voltage-Mode control
Line feed-forward PWM ramp
Internal 105V rated start-up bias regulator
Programmable line Under-Voltage Lockout (UVLO) with
adjustable hysteresis
Versatile dual mode over-current protection
Programmable volt-second limiter
Programmable soft-start
Programmable synchronous rectifier soft-start and stop
Precise 500mV over-current comparator
Current sense leading edge blanking
Programmable oscillator with 1 MHz maximum frequency
and synchronization capability
Precision 5V reference
Programmable time delays between outputs
Packages
eTSSOP-20
Typical Application Circuit
Simplified Active Clamp Converter
© 2009 National Semiconductor Corporation 300990
30099001
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LM5027 pdf, 数据表
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Time2 Delay vs RTIME2 (kΩ)
Time3 Delay vs RTIME3 (kΩ)
30099030
Time1 Delay vs Temperature
RTIME1 = 33.2 k
30099031
Time2 Delay vs Temperature
RTIME2 = 28.7 k
30099032
Time3 Delay vs Temperature
RTIME3 = 29.4 k
30099033
SS Pin Current vs Temperature
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30099034
8
30099035







LM5027 equivalent, schematic
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Fault/Event
UVLO<0.4V
Vcc
>6.2V
2.0V<UVLO
>0.4V
>6.2V
SS< 1V
>6.2V
SSSR <2.0V
OTP
<1.25V
>6.2V
>6.2V
UVLO
-
-
>2.0V
>2.0V
>2.0V
TABLE 1. Fault/Event Summary
OTP
>1.25V
>1.25V
>1.25V
>1.25V
-
SS
Fast
discharge
Fast
discharge
after
SSSR<2V
-
>4.0V
Fast
discharge
after
SSSR<2V
SSSR
Fast
discharge
Slow
discharge
Fast
discharge
-
Slow
discharge
OUTA
Low
Low
Low
Switching
Low
OUTB
Low
Low
Low
Switching
Low
OUTSR
Low
Low
Low
Low
Low
PWM Comparators
The pulse width modulator (PWM) comparator compares the
voltage ramp signal at the RAMP pin to the loop error signal.
The loop error signal is received from the external feedback
and isolation circuit in the form of a control current into the
matched pair of NPN transistors which sink current through a
5 kresistor connected to the 5V reference. The resulting
control voltage is compared at the PWM input to a 1V level
shifted ramp signal. An opto-coupler detector can be con-
nected directly between the REF pin and the COMP pin. Since
the COMP pin is a current mirror input, the potential difference
across the opto-coupler detector is nearly constant. The
bandwidth limiting phase delay which is normally introduced
by the significant capacitance of the opto-coupler is thereby
greatly reduced. Higher loop bandwidths can be realized
since the bandwidth-limiting pole associated with the opto-
coupler is now at a much higher frequency. The PWM com-
parator polarity is configured such that with no current into the
COMP pin, the controller produces maximum duty cycle at the
main gate drive output (OUTA).
Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to
VIN, AGND, and the RAMP pins is required to create the
PWM ramp signal as shown in Figure 8. The slope of the sig-
nal at the RAMP pin will vary in proportion to the input line
voltage. This varying slope provides line feed-forward infor-
mation necessary to improve line transient response with
voltage mode control. The RAMP signal is compared to the
error signal by the pulse width modulator comparator to con-
trol the duty cycle of the outputs. With a constant error signal,
the on-time (tON) varies inversely with the input voltage (VIN)
to stabilize the volt-second product of the transformer prima-
ry. The power path gain of the conventional voltage-mode
pulse with modulator (oscillator generated ramp) varies di-
rectly with input voltage. The use of a line generated ramp
(input voltage feed-forward) nearly eliminates the gain varia-
tion. As a result, the feedback loop is only required to make
very small corrections for large changes in input voltage. At
the end of each clock period, an internal MOSFET with an
RDS(ON) of 10Ω (typical) is enabled to reset the CFF capacitor
voltage to ground.
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