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PDF ( 数据手册 , 数据表 ) AD9272

零件编号 AD9272
描述 Octal LNA/VGA/AAF/ADC and Crosspoint Switch
制造商 Analog Devices
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AD9272 数据手册, 描述, 功能
FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 0.75 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 80 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)
120 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9272 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA), an antialiasing
filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 80 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9272
FUNCTIONAL BLOCK DIAGRAM
LOSW-A
LO-A
LI-A
LG-A
LNA
VGA
LOSW-B
LO-B
LI-B
LG-B LNA VGA
LOSW-C
LO-C
LI-C
LG-C LNA VGA
LOSW-D
LO-D
LI-D
LG-D
LNA
VGA
LOSW-E
LO-E
LI-E
LG-E
LNA
VGA
LOSW-F
LO-F
LI-F
LG-F LNA VGA
LOSW-G
LO-G
LI-G
LG-G
LNA
VGA
LOSW-H
LO-H
LI-H
LG-H LNA VGA
SWITCH
ARRAY
AD9272
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTA+
DOUTA–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTB+
DOUTB–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTC+
DOUTC–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTD+
DOUTD–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTE+
DOUTE–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTF+
DOUTF–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTG+
DOUTG–
AAF
12-BIT
ADC
REFERENCE
SERIAL
LVDS
DOUTH+
DOUTH–
FCO+
FCO–
DCO+
DCO–
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 0.85 nV/√Hz at maximum
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 92 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.







AD9272 pdf, 数据表
AD9272
AD9272-40
Parameter 1
Conditions
Min Typ
IAVDD1
Full-channel
mode
210
CW Doppler mode
with four channels
enabled
32
IAVDD2
Full-channel mode
365
CW Doppler mode
with four channels
enabled
140
IDRVDD
Total Power
Dissipation
Includes output
drivers, full-
channel mode, no
signal
49
1560
CW Doppler mode
with four channels
enabled
475
Power-Down
Dissipation
Standby Power
Dissipation
Power Supply
Rejection Ratio
(PSRR)
1.6
ADC RESOLUTION
12
ADC REFERENCE
Output Voltage Error VREF = 1 V
Load Regulation
At 1.0 mA,
VREF = 1 V
2
Input Resistance
6
AD9272-65
Max Min Typ
280
32
365
140
1713
51
1690
475
5
175
1.6
12
±20
2
6
AD9272-80
Max Min Typ
335
32
365
140
1860
52
1780
475
5
200
1.6
12
±20
2
6
Max Unit
mA
mA
mA
mA
mA
1975 mW
mW
5 mW
210 mW
mV/V
Bits
±20 mV
mV
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 SE = single-ended.
3 AAF settings < 5 MHz are out of range and not supported.
4 The overrange condition is specified as being 6 dB more than the full-scale input range.
Rev. C | Page 7 of 44







AD9272 equivalent, schematic
AD9272
TYPICAL PERFORMANCE CHARACTERISTICS
fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = fSAMPLE/4.5, HPF = LPF
cutoff/20.7 (default), unless otherwise noted.
2.0 25
1.5
20
1.0
0.5 –40°C
+25°C
0 +85°C
–0.5
15
10
–1.0
–1.5
–2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
GAIN+ (V)
Figure 5. Gain Error vs. GAIN+ at Three Temperatures
1.6
5
0
GAIN ERROR (dB)
Figure 8. Gain Error Histogram, GAIN+ = 1.44 V
25
20
15
10
5
0
GAIN ERROR (dB)
Figure 6. Gain Error Histogram, GAIN+ = 0.16 V
25
20
15
10
5
0
–1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
Figure 9. Gain Match Histogram, GAIN+ = 0.3 V
14
12
10
8
6
4
2
0
GAIN ERROR (dB)
Figure 7. Gain Error Histogram, GAIN+ = 0.8 V
25
20
15
10
5
0
–1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
Figure 10. Gain Match Histogram, GAIN+ = 1.3 V
Rev. C | Page 15 of 44










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