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PDF ( 数据手册 , 数据表 ) ADV3202

零件编号 ADV3202
描述 (ADV3202 / ADV3203) 32 X 16 Buffered Analog Crosspoint Switch
制造商 Analog Devices
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ADV3202 数据手册, 描述, 功能
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FEATURES
Large, 32 × 16, nonblocking switch array
G = +1 (ADV3202) or G = +2 (ADV3203) operation
32 × 32 pin-compatible version available (ADV3200/ADV3201)
Single +5 V, dual ±2.5 V, or dual ±3.3 V supply (G = +2)
Serial programming of switch array
2:1 OSD insertion mux per output
Input sync-tip clamp
High impedance output disable allows connection of
multiple devices with minimal output bus load
Excellent video performance
60 MHz 0.1 dB gain flatness
0.1% differential gain error (RL = 150 Ω)
0.1° differential phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: >300 MHz
Slew rate: >400 V/μs
Low power: 1 W
Low all hostile crosstalk: −48 dB @ 5 MHz
Reset pin allows disabling of all outputs
Connected through a capacitor to ground, provides
power-on reset capability
176-lead exposed pad LQFP package (24 mm × 24 mm)
APPLICATIONS
CCTV surveillance
Routing of high speed signals, including
Composite video (NTSC, PAL, S, SECAM)
RGB and component video routing
Compressed video (MPEG, wavelet)
Video conferencing
GENERAL DESCRIPTION
The ADV3202/ADV3203 are 32 × 16 analog crosspoint switch
matrices. They feature a selectable sync-tip clamp input for
ac-coupled applications and a 2:1 on-screen display (OSD)
insertion mux. With −48 dB of crosstalk and −80 dB isolation
at 5 MHz, the ADV3202/ADV3203 are useful in many high
density routing applications. The 0.1 dB flatness out to 60 MHz
makes the ADV3202/ADV3203 ideal for both composite and
component video switching.
The 16 independent output buffers of the ADV3202/ADV3203
can be placed into a high impedance state for paralleling cross-
point outputs so that off-channels present minimal loading to
300 MHz, 32 × 16 Buffered
Analog Crosspoint Switch
ADV3202/ADV3203
FUNCTIONAL BLOCK DIAGRAM
VPOS VNEG DVCC DGND
CLK
DATA IN
193-BIT SHIFT REGISTER
UPDATE
CS
RESET
ENABLE/
BYPASS
97 96
PARALLEL LATCH
96
16 × 5:32
DECODERS
ADV3202
(ADV3203)
16 ENABLE/
DISABLE
SYNC-TIP
CLAMP
512
OUTPUT
BUFFER
G = +1
(G = +2)
DATA
OUT
32
INPUTS
...
...
SWITCH OSD
... ...MATRIX MUX
16
OUTPUTS
16
REFERENCE
16
VCLAMP
OSD
OSD VREF
INPUTS SWITCHES
Figure 1.
an output bus if building a larger array. The ADV3202 has a
gain of +1 while the ADV3203 has a gain of +2 for ease of use in
back-terminated load applications. A single +5 V supply, dual
±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used
while consuming only 195 mA of idle current with all outputs
enabled. The channel switching is performed via a double
buffered, serial digital control that can accommodate daisy
chaining of several devices.
The ADV3202/ADV3203 are packaged in a 176-lead exposed
pad LQFP package (24 mm× 24 mm) and are available over the
extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.







ADV3202 pdf, 数据表
wwAwD.DVat3aS2h0ee2t4/UA.cDomV3203
Table 7. Pin Function Descriptions
Pin Mnemonic Description
1 DVCC
Digital Positive Power Supply.
2 NC
No Connect.
3 RESET
Control Pin: 1st and 2nd Rank Reset.
4 CLK
Control Pin: Serial Data Clock.
5 DATA IN
Control Pin: Serial Data In.
6
DATA OUT
Control Pin: Serial Data Out.
7 UPDATE
Control Pin: Second Rank Write Strobe.
8 CS
Control Pin: Chip Select.
9 DGND
Digital Negative Power Supply.
10 IN00
Input Number 0.
11 DGND
Digital Negative Power Supply.
12 IN01
Input Number 1.
13 DGND
Digital Negative Power Supply.
14 IN02
Input Number 2.
15 DGND
Digital Negative Power Supply.
16 IN03
Input Number 3.
17 DGND
Digital Negative Power Supply.
18 IN04
Input Number 4.
19 DGND
Digital Negative Power Supply.
20 IN05
Input Number 5.
21 DGND
Digital Negative Power Supply.
22 IN06
Input Number 6.
23 DGND
Digital Negative Power Supply.
24 IN07
Input Number 7.
25 DGND
Digital Negative Power Supply.
26 IN08
Input Number 8.
27 DGND
Digital Negative Power Supply.
28 IN09
Input Number 9.
29 DGND
Digital Negative Power Supply.
30 IN10
Input Number 10.
31 DGND
Digital Negative Power Supply.
32 IN11
Input Number 11.
33 DGND
Digital Negative Power Supply.
34 IN12
Input Number 12.
35 DGND
Digital Negative Power Supply.
36 IN13
Input Number 13.
37 DGND
Digital Negative Power Supply.
38 IN14
Input Number 14.
39 DGND
Digital Negative Power Supply.
40 IN15
Input Number 15.
41 VNEG
Analog Negative Power Supply.
42 VREF
Reference Voltage. See the Theory of
Operation section for details.
43 VCLAMP
Sync-Tip Clamp Voltage. See the
Theory of Operation section for details.
44 OSD15
OSD Input Number 15.
45 OSD14
OSD Input Number 14.
46 OSD13
OSD Input Number 13.
47 OSD12
OSD Input Number 12.
48 OSD11
OSD Input Number 11.
49 OSD10
OSD Input Number 10.
Pin Mnemonic
50 OSD09
51 OSD08
52 VPOS
53 OUT15
54 VNEG
55 OUT14
56 VPOS
57 OUT13
58 VNEG
59 OUT12
60 VPOS
61 OUT11
62 VNEG
63 OUT10
64 VPOS
65 OUT09
66 VNEG
67 OUT08
68 VPOS
69 OUT07
70 VNEG
71 OUT06
72 VPOS
73 OUT05
74 VNEG
75 OUT04
76 VPOS
77 OUT03
78 VNEG
79 OUT02
80 VPOS
81 OUT01
82 VNEG
83 OUT00
84 VPOS
85 OSD07
86 OSD06
87 OSD05
88 OSD04
89 VNEG
90 OSD03
91 OSD02
92 OSD01
93 OSD00
94 VPOS
95 IN31
96 OSDS15
97 IN30
98 OSDS14
99 IN29
100 OSDS13
Description
OSD Input Number 9.
OSD Input Number 8.
Analog Positive Power Supply.
Output Number 15.
Analog Negative Power Supply.
Output Number 14.
Analog Positive Power Supply.
Output Number 13.
Analog Negative Power Supply.
Output Number 12.
Analog Positive Power Supply.
Output Number 11.
Analog Negative Power Supply.
Output Number 10.
Analog Positive Power Supply.
Output Number 9.
Analog Negative Power Supply.
Output Number 8.
Analog Positive Power Supply.
Output Number 7.
Analog Negative Power Supply.
Output Number 6.
Analog Positive Power Supply.
Output Number 5.
Analog Negative Power Supply.
Output number 4.
Analog Positive Power Supply.
Output Number 3.
Analog Negative Power Supply.
Output Number 2.
Analog Positive Power Supply.
Output Number 1.
Analog Negative Power Supply.
Output Number 0.
Analog Positive Power Supply.
OSD Input Number 7.
OSD Input Number 6.
OSD Input Number 5.
OSD Input Number 4.
Analog Negative Power Supply.
OSD Input Number 3.
OSD Input Number 2.
OSD Input Number 1.
OSD Input Number 0.
Analog Positive Power Supply.
Input Number 31.
Control Pin: OSD Select Number 15.
Input Number 30.
Control Pin: OSD Select Number 14.
Input Number 29.
Control Pin: OSD Select Number 13.
Rev. 0 | Page 8 of 20







ADV3202 equivalent, schematic
wwAwD.DVat3aS2h0ee2t4/UA.cDomV3203
APPLICATIONS INFORMATION
PROGRAMMING
The ADV3202/ADV3203 are programmed serially through a
193-bit serial word that updates the matrix and the state of the
sync-tip clamps each time the part is programmed.
Serial Programming Description
The serial programming mode uses the CLK, DATA IN,
UPDATE, and CS device pins. The first step is to assert a low
on CS to select the device for programming. The UPDATE
signal should be high during the time that data is shifted into
the serial port of the device. Although the data still shifts in
when UPDATE is low, the transparent, asynchronous latches
allow the shifting data to reach the matrix. This causes the
matrix to try to update to every intermediate state as defined by
the shifting data.
The data at DATA IN is clocked in at every rising edge of CLK.
A total of 193 bits must be shifted in to complete the program-
ming. For each of the 16 outputs, there are five bits (D0 to D4)
that determine the source of its input followed by one bit (D5)
that determines the enabled state of the output. If D5 is low
(output disabled), the five associated bits (D0 to D4) do not
matter because no input is switched to that output. These
comprise the first 96 bits of DATA IN. The remaining 96 bits of
DATA IN should be set to zero. If a string of 96 zeros is not
suffixed to the first 96 bits of DATA IN, a certain test mode is
employed that can cause the device to draw up to 30% more
current. The last bit, Bit 193, is used to enable or disable the
sync-tip clamps. If Bit 193 is low, the sync-tip clamps are
disabled; otherwise, they are enabled.
The sync-tip clamp bit is shifted in first, followed by the most
significant output address data (OUT15). The enable bit (D5) is
shifted in first, followed by the input address (D4 to D0) entered
sequentially with D4 first and D0 last. Each remaining output is
programmed sequentially, until the least significant output
address data is shifted in. At this point, UPDATE can be taken
low, which causes the programming of the device according to
the data that was just shifted in. The UPDATE latches are
asynchronous and when UPDATE is low, they are transparent.
If more than one ADV3202/ADV3203 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK and UPDATE pins should be
connected in parallel and operated as described previously. The
serial data is input to the DATA IN pin of the first device of the
chain, and it ripples through to the last. Therefore, the data for
the last device in the chain should come at the beginning of the
programming sequence. The length of the programming
sequence is 193 bits times the number of devices in the chain.
Reset
When powering up the ADV3200/ADV3201, it is often useful
to have the outputs come up in the disabled state. The RESET
pin, when taken low, causes all outputs to be disabled. After
power-up, the UPDATE pin should be driven high prior to
raising RESET.
Because the data in the shift register is random after power-up,
it should not be used to program the matrix, or the matrix may
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE initially after power-up. The shift register
should first be loaded with data and UPDATE then taken low to
program the device.
The RESET pin has a 25 kΩ pull-up resistor to DVCC that can
be used to create a simple power-on reset circuit. A capacitor
from RESET to ground holds RESET low for some time while
the rest of the device stabilizes. The low condition causes all the
outputs to be disabled. The capacitor then charges through the
pull-up resistor to the high state, thus allowing full programming
capability of the device.
The CS pin has a 25 kΩ pull-down resistor to ground.
Rev. 0 | Page 16 of 20










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