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PDF ( 数据手册 , 数据表 ) TJA1082

零件编号 TJA1082
描述 FlexRay Node Transceiver
制造商 NXP Semiconductors
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TJA1082 数据手册, 描述, 功能
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TJA1082
FlexRay node transceiver
Rev. 01 — 1 July 2009
Preliminary data sheet
1. General description
The TJA1082 FlexRay node transceiver is compatible with the FlexRay electrical physical
layer specification V2.1 Rev. B (see Ref. 1). It also incorporates features and parameters
anticipated to be included in V3.0, currently being finalized. It is primarily intended for
communication systems operating at between 2.5 Mbit/s and 10 Mbit/s, and provides an
advanced interface between the protocol controller and the physical bus in a FlexRay
network. The TJA1082 offers an optimized solution for Electronic Control Unit (ECU)
applications that do not need enhanced power management and are typically switched by
ignition or activated by a dedicated wake-up line.
The TJA1082 provides differential transmit capability to the network and differential
receive capability to the FlexRay controller. It offers excellent EMC performance as well as
high ESD protection.
The TJA1082 actively monitors system performance using dedicated error and status
information (readable by any microcontroller), as well as internal voltage and temperature
monitoring.
2. Features
2.1 Optimized for time triggered communication systems
I Compliant with Electrical Physical Layer specification 2.1 Rev. B
I Automotive product qualification in accordance with AEC-Q100 (Grade 1)
I Data transfer at 2.5 Mbit/s, 5 Mbit/s and 10 Mbit/s
I Supports 60 ns minimum bit time at 400 mV differential voltage
I Very low ElectroMagnetic Emission (EME) to support unshielded cable
I Differential receiver with high common-mode range for excellent ElectroMagnetic
Immunity (EMI)
I Auto I/O level adaptation to host controller supply voltage VIO
I Can be used in 14 V and 42 V powered systems
I Instant shut down interface (BGE pin)
2.2 Low power management
I Very low current consumption in Standby mode
I Remote wake-up via wake-up symbol or dedicated FlexRay data frames on the bus
lines







TJA1082 pdf, 数据表
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TJA1082
FlexRay node transceiver
NORMAL
(STBN -> HIGH while
UV flags cleared) or
(UV flags cleared while
STBN = HIGH)
STBN -> LOW or
UVVCC flag set or
UVVIO flag set
STANDBY
VCC > Vth(rec)POR
VCC < Vth(det)POR
power-up
Fig 4. State transitions diagram
POWER OFF
015aaa004
20 µs
STBN
ERRN
td(norm-stb)
Fig 5. State transitions timing (bus error flag set)
TJA1082_1
Preliminary data sheet
Rev. 01 — 1 July 2009
td(stb-norm)
015aaa003
© NXP B.V. 2009. All rights reserved.
8 of 35







TJA1082 equivalent, schematic
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TJA1082
FlexRay node transceiver
SCSN
(V) VIO
SPI mode
simple error
indication mode
SPI mode
0
SCLK
(V) VIO
t
0
t
tdet(L)(SCLK)
Fig 11. State transitions timing (bus error flag set)
015aaa015
If an undervoltage condition is detected, it will not be possible to switch between SPI
mode and simple error indication mode.
6.7.1 SPI mode
The error flag information in the status register is latched in SPI mode. This means that
the status bit is reset once the status register has been completely read out (provided the
corresponding error flag has been reset). If an error condition is detected in Normal mode,
pin ERRN goes LOW (provided one of the error bits, S5-S10, is set). Pin ERRN goes
HIGH again once all the error bits (S5-S10) have been reset.
6.7.2 Simple error indication mode
If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant
error flag has been set. Pin ERRN goes HIGH again when all error conditions have been
cleared and all flags have been reset. Error flags are not latched. It is not possible to
read-out the status bits in this mode.
6.8 SPI interface
The TJA1082 includes a 16-bit SPI interface to enable a host to read the status register
when the transceiver is in SPI mode (see Section 6.7).
While pin SCSN is HIGH, the SDO output will be in a high-impedance state. To begin a
status register readout, the host must force pin SCSN LOW. This will cause the SDO pin
to output a LOW level by default. The data at pin SDO is then shifted out on the rising
edge of the clock signal on pin SCLK.
The status bits shifted out at SDO are active HIGH. The status bits are refreshed and pin
SDO returned to a high-impedance state once the status register has been read
successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock
signals on SCLK will be ignored while SCSN is HIGH. The timing diagram for the SPI
readout is illustrated in Figure 12.
The SLCK period ranges from 500 ns to100 µs (10 kbit/s to 2 Mbit/s)
TJA1082_1
Preliminary data sheet
Rev. 01 — 1 July 2009
© NXP B.V. 2009. All rights reserved.
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