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PDF ( 数据手册 , 数据表 ) ZL30143

零件编号 ZL30143
描述 SyncE SONET/SDH G.8262/Stratum3 System Synchronizer/SETS
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL30143 数据手册, 描述, 功能
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ZL30143
SyncE SONET/SDH
G.8262/Stratum3 System Synchronizer/SETS
Short Form Data Sheet
Features
• Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
• Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.813, and G.781
SETS
• Supports ITU-T G.823, G.824 and G.8261 for 2048
kbit/s and 1544 kbit/s interfaces
• Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
• Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
• Supports composite clock inputs (64 kHz, 64 kHz +
8 kHz, 64kHz + 8 kHz + 400 Hz)
• Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
• Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz
• Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
• Provides two DPLLs which are independently
configurable through a serial interface
February 2009
Ordering Information
ZL30143GGG 100 Pin CABGA
ZL30143GGG2 100 Pin CABGA*
*Pb Free Tin/Silver/Copper
-40oC to +85oC
Trays
Trays
• Internal state machine automatically controls
mode of operation (free-run, locked, holdover)
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Provides automatic reference switching and
holdover during loss of reference input
• Supports master/slave configuration and dynamic
input to output delay compensation for
AdvancedTCATM
• Configurable input to output delay and output to
output phase alignment
Applications
• ITU-T G.8262 System Timing Cards which support
1 GbE and 10 GbE interfaces
• Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
• System Timing Cards which supports ITU-T G.781
SETS (SDH Equipment Timing Source)
dpll2_ref
osci osco
refm
DPLL2
T4
P1
S yn th e s iz e r
p1_clk0
p1_clk1
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
ref8
sync0
sync1
sync2
sync8
/N1
/N2
Input
Ports
Ref/Sync
Monitors
refn/syncn
DPLL1
T0
P0
S yn th e s iz e r
SONET/SDH/
Ethernet
APLL
Feedback
S yn th e s iz e r
mode lock hold
I2C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
p0_clk0
p0_clk1
p0_fp0
p0_fp1
diff0
diff1
apll_clk0
apll_clk1
apll_fp0
apll_fp1
fb_clk
ext_fb_clk
ext_fb_fp












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