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PDF ( 数据手册 , 数据表 ) SX1210

零件编号 SX1210
描述 Ultra-Low Power Integrated UHF Receiver
制造商 Semtech Corporation
LOGO Semtech Corporation LOGO 


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SX1210 数据手册, 描述, 功能
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ADVANCED COMMUNICATIONS & SENSING
General Description
The SX1210 is a low cost single-chip receiver
operating in the frequency ranges from 863-870, 902-
928 MHz and 950-960 MHz. The SX1210 is optimized
for very low power consumption (3mA). It incorporates
a baseband demodulator with data rates up to 200
kb/s. Data handling features include a sixty-four byte
FIFO, packet handling, CRC and data whitening
processing. Its highly integrated architecture allows for
minimum external component count whilst maintaining
design flexibility. All major RF communication
parameters are programmable and most of them may
be dynamically set. It complies with European (ETSI
EN 300-220 V2.1.1) and North American (FCC part
15.247 and 15.249) regulatory standards.
Ordering Information
Table 1: Ordering Information
Part number
Delivery
Minimum Order
Quantity / Multiple
SX1210I084TRT Tape & Reel
3000 pieces
ƒ
ƒ TQFN-32 package – Operating range [-40;+85°C]
ƒ T refers to Lead Free packaging
ƒ This device is WEEE and RoHS compliant
Application Circuit Schematic
SX1210 Receiver
Ultra-Low Power Integrated UHF Receiver
Features
ƒ Low Rx power consumption: 3mA
ƒ Good reception sensitivity: down to -107 dBm at
25 kb/s in FSK, -113 dBm at 2kb/s in OOK
ƒ Packet handling feature with data whitening and
CRC processing
ƒ RSSI (Received Signal Strength Indicator) range
from Rx noise floor to 0 dBm
ƒ Bit rates up to 200 kb/s, NRZ coding
ƒ On-chip frequency synthesizer
ƒ FSK and OOK modulation
ƒ Incoming sync word recognition
ƒ Built-in Bit-Synchronizer for incoming data and
clock synchronization and recovery
ƒ 5 x 5 mm TQFN package
ƒ Optimized Circuit Configuration for Low-cost
applications
ƒ Pin to pin compatible with SX1211 Transceiver
Applications
ƒ Wireless alarm and security systems
ƒ Wireless sensor networks
ƒ Automated Meter Reading
ƒ Home and building automation
ƒ Industrial monitoring and control
ƒ Remote Wireless Control
Rev 2– Sept 8th, 2008
Page 1 of 73
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SX1210 pdf, 数据表
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ADVANCED COMMUNICATIONS & SENSING
SX1210
2. Electrical Characteristics
2.1. ESD Notice
The SX1210 is a high performance radio frequency device. It satisfies:
ƒ Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model), except on pins 3-4-5-27-28-31-where it
satisfies Class 1A.
ƒ Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins.
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Table 3: Absolute Maximum Ratings
Symbol
VDDmr
Tmr
Pmr
Description
Supply voltage
Storage temperature
Input level
Min Max
-0.3 3.7
-55 125
-0
Unit
V
°C
dBm
2.3. Operating Range
Table 4: Operating Range
Symbol
VDDop
Trop
ML
Description
Supply Voltage
Temperature
Input Level
Min Max Unit
2.1 3.6 V
-40 +85 °C
- 0 dBm
2.4. Chip Specification
Conditions: Temp = 25 °C, VDD = 3.3 V, crystal frequency = 12.8 MHz, carrier frequency = 869 or 915 MHz,
modulation FSK, data rate = 25 kb/s, Fdev = 50 kHz, fc = 100 kHz, unless otherwise specified.
2.4.1. Power Consumption
Table 5: Power Consumption Specification
Symbol
Description
Conditions
IDDSL
Supply current in sleep
mode
IDDST
Supply current in standby
mode, CLKOUT disabled
Crystal oscillator running
IDDFS
Supply current in FS mode
Frequency synthesizer
running
IDDR
Supply current in receiver
mode
(1) Guaranteed by design and characterization
Min Typ Max Unit
- 0.1 2 µA
- 65 95 µA
- 1.3 1.7 mA
- 3.0 3.5 mA
Rev 2– Sept 8th, 2008
Page 8 of 73
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SX1210 equivalent, schematic
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ADVANCED COMMUNICATIONS & SENSING
RL1
CL2 CL1
LF_M
LF_P
SX1210
Figure 7: Loop Filter
Following the recommendations made in section 3.2.4, the loop filter proposed in the reference design’s bill of
material on section 7.5.3 should be used. The loop filter settings are frequency band independent and are hence
relevant to all implementations of the SX1210.
3.2.7. PLL Lock Detection Indicator
The SX1210 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting
the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions.
The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a “1” to this same register.
In addition, the lock status can be reflected in pin 23 PLL_LOCK, by setting the bit IRQParam_Enable_lock_detect.
3.2.8. Frequency Calculation
As shown in Figure 5 the PLL structure comprises three different dividers, R, P and S, which set the output
frequency through the LO. A second set of dividers is also available to allow rapid switching between a pair of
frequencies: R1/P1/S1 and R2/P2/S2. These six dividers are programmed by six bytes of the register MCParam
from addresses 6 to 11.
3.2.8.1. FSK Mode
The following formula gives the relationship between the local oscillator, and R, P and S values, when using FSK
modulation.
Frf , fsk = 9 Flo
8
Frf , fsk = 9 Fxtal [75(P + 1) + S )]
8 R +1
3.2.8.2. OOK Mode
Due to the low intermediate frequency (Low-IF) architecture of the SX1210 the frequency should be configured so
as to ensure the correct low-IF receiver baseband center frequency, IF2.
Frf ,ook = 9 Flo IF 2
8
Frf ,ook = 9 Fxtal [75(P +1) + S )]IF 2
8 R +1
Note that from Section 3.3.4, it is recommended that IF2 be set to 100 kHz.
Rev 2– Sept 8th, 2008
Page 16 of 73
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