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PDF ( 数据手册 , 数据表 ) IP1000ALF

零件编号 IP1000ALF
描述 Gigabit Ethernet NIC Single Chip
制造商 IC Plus
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IP1000ALF 数据手册, 描述, 功能
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IP1000A LF
Preliminary Data Sheet
Gigabit Ethernet NIC Single Chip
Features
PCI & DMA Features
– PCI Specification Revision 2.3 compliant
– 32-bit, 33/66MHz bus master capability
– Efficient DMA operation maximizes PCI
band-width utilization
– 1 Terabyte (40 bit) address space
– Scatter, gather transmit/receive DMA
– Transmit "interrupt-less" mode of
operation
– Receive frame priority interrupts
– Receive interrupt coalescing
FIFO Features
– No external memory required
– Receive FIFO flow control thresholds
– Configurable TX/RX FIFO
MAC Features
– IEEE 802.3z, 802.3x compliant
– IEEE 802.1p, 802.1Q compliant
– 1000Mbps, 100Mbps, 10Mbps triple
speed, half/full duplex operation
– Transmit and receive back to back frames
at full wire speed
– Half duplex carrier extension and packet
bursting
– Asymmetric/symmetric flow control
– VLAN tag insertion/removal
– VLAN tagged frame filtering
– IPV4/6, TCP, UDP checksum calculation/
verification
– 802.3 MIB statistic register sets
– 64-bit hash table for multicast frame
filtering
– Jumbo frame support for transmit/receive
– Big-endian
Phsical Layer Features
– Fully integrated IEEE 802.3ab compliant
1000BASE-T, 100BASE-TX and
10BASE-T port
– DSP receiver includes feed-forward
equalizer, decision feedback equalizer,
echo canceller, crosstalk canceller, and
baseline wander correction
– 802.3ab compliant Auto-Negotiation for
automatic speed, duplex, and
master/slave configuration
– Automatic MDI/MDI-X crossover function
and polarity correction
– Automatic pair skew adjustment
– PHY management registers
– Smart Cable Analyzer (SCA™)
– Smart speed downshift
– APS(Auto Power Saving)
a. Power Saving with Link status detecting
b. Keep only MAC alive through
software setting
Power Management, EEPROM and Package
– WakeOnLAN support
– ACPI Revision 1.0 compliant
– 1.8/3.3V CMOS with 5V tolerant I/O
– EEPROM 93C46 support
– Optional boot from serial ROM support
– 128-pin LQFP with e-PAD package
Support Lead Free package (Please refer to
the Order Information)
General Description
The IP1000A LF is a truly 10/100/1000Mbps
Gigabit Ethernet NIC single chip which it
incorporates a 32-bit PCI interface with bus
master support. It is manufactured using standard
digital CMOS process and contains all the active
circuitry required to implement the physical layer
functions to transmit and receive data on standard
CAT5 unshielded twisted pair cable.
The IP1000A LF is designed for use in a variety of
applications including workstation NICs, and other
systems utilizing a PCI bus.
The IP1000A LF includes a 32-bit PCI bus
interface, IEEE 802.3 compliant MAC, transmit
and receive FIFO buffers, IEEE 802.3 compliant
10BASE-T, and 100BASE-TX PHY, IEEE 802.3z
compliant 1000 BASE-T PHY, serial EEPROM
interface, expansion ROM interface and LED
drivers.
The IP1000A LF supports features for use in
“Green PCs” or systems where control over
system power consumption is desired. The
IP1000A LF supports several power down states,
and the ability to issue a system “wake event” via
reception of unique, user defined Ethernet frames.
In addition, the IP1000A LF can assert a wake
event in response to changes in the Ethernet link
status.
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IP1000ALF pdf, 数据表
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PIN Description (continued)
IP1000A LF
Preliminary Data Sheet
Pin no.
Label
PCI interface (continued)
101 IRDYN
104 STOPN
103 DEVSELN
82 IDSEL
67 PCICLK
105 PERRN
107 SERRN
68 REQN
62 GNTN
80, 96, 112, CBE [3:0] N
125
Type
Description
I/O Initiator Ready, asserted LOW.
A bus master asserts IRDYN to indicate valid data phases
on AD during write data phases, and to indicate it is ready to
accept data during read data phases. A target will monitor
IRDYN.
I/O Stop, asserted LOW.
STOPN is driven by the slave target to inform the bus
master to terminate the current transaction.
I/O Device Select, asserted LOW.
The IP1000A LF asserts DEVSELN when it is selected as a
target during a bus transaction. It monitors DEVSELN for
any target to acknowledge a bus transaction initiated by the
IP1000A LF.
I Initialization Device Select.
The IDSEL is used to select the IP1000A LF during
configuration read and write transactions.
I PCI Bus Clock.
This clock is used to drive the PCI bus interfaces and the
internal DMA logic. All bus signals are sampled on the rising
edge of PCICLK. PCICLK can operate from 0MHz to
66MHz, on a PCI bus.
I/O Parity Error, asserted LOW.
The IP1000A LF asserts PERRN when it checks and
detects a bus parity error. When it is generating PAR output,
the IP1000A LF monitors for any reported parity error on
PERRN.
O System Error, asserted LOW.
O Request, asserted LOW.
The IP1000A LF asserts REQN to request PCI bus master
operation.
I PCI Bus Grant, asserted LOW.
GNTN signals access to the PCI bus has been granted to
IP1000A LF.
I/O PCI Bus Command/Byte Enable, asserted LOW.
Bus command and byte enables are multiplexed on the
CBEN signals. CBEN specify the bus command during the
address phase transaction, and carry byte enables during
the data phase.
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IP1000A LF
Preliminary Data Sheet
2.2.5.1 Power Management States
The IP1000A LF supports several power management states. The PowerState field in the
PowerMgmtCtrl register determines IP1000A LF’s current power state. The power states are defined as
follows:
D0 Uninitialized (power state 0) is entered as a result of hardware reset, or after a transition from D3
Hot to D0. This state is the same as D0 Active except that the PCI configuration registers are
uninitialized. In this state, the IP1000A LF responds to PCI configuration cycles only.
D0 Active (power state 0) is the normal operational power state for the IP1000A LF. In this state, the
PCI configuration registers have been initialized by the system, including the IoSpace,
MemorySpace, and BusMaster bits in the ConfigCommand register, so the IP1000A LF is able to
respond to PCI I/O, memory and configuration cycles and can operate as a PCI master. The
IP1000A LF cannot signal wake (PMEN on the PCI bus) from the D0 state.
D1 (power state 1) is a “light-sleep” state. The IP1000A LF optionally supports this state determined
by the D1Support bit in the ConfigParm word in the EEPROM. The D1 state allows transition back to
D0 with no delay. In this state, the IP1000A LF responds to PCI configuration accesses, to allow the
system to change the power state. The IP1000A LF’s function in the D1 state is to recognize wake
events and link state events and pass them on to the system by asserting the PMEN signal on the
PCI bus.
D2 (power state 2) is a partial power-down state. The IP1000A LF optionally supports this state
determined by the D2Support bit in the ConfigParm word in the EEPROM. D2 allows a faster
transition back to D0 than is possible from the D3 state. In this state, the IP1000A LF responds to
PCI configuration accesses, to allow the system to change the power state. In D2 the IP1000A LF
does not respond to any PCI I/O or memory accesses. The IP1000A LF’s function in the D2 state is
to recognize wake events and link state events and pass them on to the system by asserting the
PMEN signal on the PCI bus.
D3 Hot (power state 3) is the full power-down state for the IP1000A LF. In this state, the IP1000A LF
responds to PCI configuration accesses, to allow the system to change the power state back to D0
Uninitialized. In D3 hot, the IP1000A LF does not respond to any PCI I/O or memory accesses. The
IP1000A LF’s main responsibility in the D3 Hot state is to recognize wake events and link state
events and signal those to the system by asserting the PMEN signal on the PCI bus.
D3 Cold (power state undefined) is the power-off state for the IP1000A LF. The IP1000A LF does not
function in this state. When power is restored, the system guarantees the assertion of hardware
reset, which puts the IP1000A LF into the D0 Uninitialized state.
2.2.6 Wake On LAN
Wake on LAN is a key component of the IBM/Intel® Advanced Manageability Alliance (AMA) initiative.
The IP1000A LF implements a portion of the Wake On LAN functionality defined by the AMA initiative.
Specifically, the IP1000A LF can be configured to respond to wake up frames sent by a Wake On LAN
managerment station.
2.2.6.1 Wake Events
The IP1000A LF can generate wake events to the system as a result of Wake Packet reception, Magic
Packet reception, or due to a change in the link status. The WakeEvent register gives the host system
control over which of these events are passed to the system. Wake events are signaled over the PCI bus
using the PMEN signal.
A Wake Packet event is controlled by the WakePktEnable bit in WakeEvent register. The WakePktEnable
bit has no effect when IP1000A LF is in the D0 power state, as the wake process can only take place in
states D1, D2, or D3. When the IP1000A LF detects a Wake Packet, it signals a wake event on PMEN (if
PMEN assertion is enabled), and sets the WakePktEvent bit in the WakeEvent register. The IP1000A LF
can signal that a wake event has occurred when it receives a pre-defined frame from another station.
The host system transfers a set of frame data patterns into the transmit FIFO using the TxDMA function
before placing the IP1000A LF in a power-down state. Once powered down, the IP1000A LF compares
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