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零件编号 | WP2002A-Y-JCS | ||
描述 | WP2002A-Y-JCS | ||
制造商 | DB Lectro | ||
LOGO | |||
1 Page
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DB LECTRO Inc.
SPECIFICATION
Ver:0
CUSTOMER :
MODULE NO.:
WP2002A-Y-JCS
APPROVED BY:
( FOR CUSTOMER USE ONLY )
SALES BY
APPROVED BY
CHECKED BY
PREPARED BY
ISSUED DATE:
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9.Functionwww.DataSheet4U.com Description
The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an
instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information
for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written
from the MPU. The DR temporarily stores data to be written or read from DDRAM or
CGRAM. When address information is written into the IR, then data is stored into the DR from
DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected.
RS R/W
Operation
0 0 IR write as an internal operation (display clear, etc.)
0 1 Read busy flag (DB7) and address counter (DB0 to DB7)
1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)
1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)
Busy Flag (BF)
When the busy flag is 1, the controller LSI is in the internal operation mode, and the next
instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7.
next instruction must be written after ensuring that the busy flag is 0.
The
Address Counter (AC)
The address counter (AC) assigns addresses to both DDRAM and CGRAM
Display Data RAM (DDRAM)
This DDRAM is used to store the display data represented in 8-bit character codes. Its extended
capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM
addresses and positions on the liquid crystal display.
High bits
Low bits
AC
(hexadecimal)
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Example: DDRAM addresses 4E
1001110
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Power on
Wait for more than 15 ms after VCC rises to 4.5 V
RS R/W DB7 DB6 DB5 DB4
000011
BF can not be checked before this instruction.
Function set ( Interface is 8 bits long. )
Wait for more than 4.1 ms
RS R/W DB7 DB6 DB5 DB4
000011
BF can not be checked before this instruction.
Function set ( Interface is 8 bits long. )
Wait for more than 100 µs
RS R/W DB7 DB6 DB5 DB4
000011
BF can not be checked before this instruction.
Function set ( Interface is 8 bits long. )
RS R/W DB7 DB6 DB5 DB4
0000 10
0000 10
0 0 NF * *
000000
00 1000
000000
000001
000000
0 0 0 1 I/D S
Initialization ends
4-Bit Ineterface
BF can be checked after the following instructions.
When BF is not checked , the waiting time between
instructions is longer than execution instruction time.
Function set ( Set interface to be 4 bits long. )
Interface is 8 bits in length.
Function set ( Interface is 4 bits long. Specify
the number of display lines and character font. )
The number of display lines and character font
can not be changed after this point.
Display off
Display clear
Entry mode set
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页数 | 18 页 | ||
下载 | [ WP2002A-Y-JCS.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
WP2002A-Y-JCS | WP2002A-Y-JCS | DB Lectro |
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