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PDF ( 数据手册 , 数据表 ) UJA1066

零件编号 UJA1066
描述 High-speed CAN fail-safe system basis chip
制造商 NXP Semiconductors
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UJA1066 数据手册, 描述, 功能
UJA1066
High-speed CAN fail-safe system basis chip
Rev. 03 — 17 March 2010
Product data sheet
1. General description
The UJA1066 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Controller Area Network
(CAN) interface. The fail-safe SBC supports all networking applications that control
various power and sensor peripherals by using high-speed CAN as the main network
interface. The fail-safe SBC contains the following integrated devices:
High-speed CAN transceiver, interoperable and downward compatible with CAN
transceiver TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard
and the ISO 11898-5 standard (in preparation)
Advanced independent watchdog
Dedicated voltage regulators for microcontroller and CAN transceiver
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and subsystem levels
The UJA1066 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide a full monitoring and
software-driven fallback operation.
The UJA1066 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.







UJA1066 pdf, 数据表
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
mode change via SPI
mode change via SPI
watchdog
trigger
Standby mode
V1: ON
SYSINH: HIGH
CAN: on-line/on-line listen/off-line
watchdog: time-out/OFF
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
mode change via SPI
watchdog
trigger
Normal mode
V1: ON
SYSINH: HIGH
CAN: all modes available
watchdog: window
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
wake-up detected with its wake-up interrupt disabled
mode change via SPI
OR mode change to Sleep with pending wake-up
OR watchdog time-out with watchdog timeout interrupt disabled
OR watchdog OFF and IV1 > IthH(V1) with reset option
OR interrupt ignored > tRSTN(INT)
OR RSTN falling edge detected
flash entry enabled (111/001/111 mode sequence)
OR mode change to Sleep with pending wake-up
OR V1 undervoltage detected
OR illegal Mode register code
OR watchdog not properly served
OR interrupt ignored > tRSTN(INT)
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
Sleep mode
V1: OFF
SYSINH: HIGH/float
CAN: on-line/on-line listen/off-line
watchdog: time-out/OFF
INH/LIMP: LOW/float
RSTN: LOW
EN: LOW
init Normal mode
via SPI successful
Start-up mode
wake-up detected
OR watchdog time-out
OR V3 overload detected
init Normal mode
via SPI successful
Restart mode
V1: ON
SYSINH: HIGH
CAN: on-line/on-line listen/off-line
watchdog: start-up
INH/LIMP: LOW/float
EN: LOW
supply connected
for the first time
V1: ON
SYSINH: HIGH
CAN: on-line/on-line listen/off-line
watchdog: start-up
INH/LIMP: HIGH/LOW/float
EN: LOW
t > tWD(init)
OR SPI clock count < > 16
OR RSTN falling edge detected
OR RSTN released and V1 undervoltage detected
OR illegal Mode register code
wake-up detected
AND oscillator ok
AND t > tret
init Flash mode via SPI
AND flash entry enabled
leave Flash mode code
OR watchdog time-out
OR interrupt ignored > tRSTN(INT)
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
watchdog
trigger
Flash mode
V1: ON
SYSINH: HIGH
CAN: all modes available
watchdog: time-out
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
t > tWD(init)
OR SPI clock count < > 16
OR RSTN falling edge detected
OR RSTN released and V1 undervoltage detected
OR illegal Mode register code
Fail-safe mode
V1: OFF
SYSINH: HIGH/float
CAN: on-line/on-line listen/off-line
watchdog: OFF
INH/LIMP: LOW
RSTN: LOW
EN: LOW
oscillator fail
OR RSTN externally clamped HIGH detected > tRSTN(CHT)
OR RSTN externally clamped LOW detected > tRSTN(CLT)
OR V1 undervoltage detected > tV1(CLT)
from any
mode
001aag305
Fig 3. Main state diagram
UJA1066_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
© NXP B.V. 2010. All rights reserved.
8 of 70







UJA1066 equivalent, schematic
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
The behavior of pin RSTN is illustrated in Figure 6. The duration of tRSTNL depends on the
setting of bit RLC (which defines the reset length). Once an external reset event has been
detected, the system controller enters Start-up mode. The watchdog now starts to monitor
pin RSTN as illustrated in Figure 7. If the RSTN pin is not released in time, the SBC will
enter Fail-safe mode (see Figure 3).
V1 Vrel(UV)(V1)
Vdet(UV)(V1)
power-up
VRSTN
under-
voltage
missing
watchdog
access
under-
voltage
spike
power-
down
time
tRSTNL
Fig 6. Reset pin behavior
tRSTNL
tRSTNL
VRSTN
time
coa054
t RSTNL
RSTN
externally
forced LOW
VRSTN
t WD (init)
time
UJA1066_2
Product data sheet
t RSTNL
RSTN externally forced LOW
Fig 7. Reset timing diagram
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
time
t WD (init)
001aad181
© NXP B.V. 2010. All rights reserved.
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