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PDF ( 数据手册 , 数据表 ) KK16C554PL

零件编号 KK16C554PL
描述 QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT
制造商 KODENSHI KOREA
LOGO KODENSHI KOREA LOGO 


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KK16C554PL 数据手册, 描述, 功能
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KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
1. General Description
KK16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter).
Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal
FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.
Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete
status of the UART at any time during the functional operation. The Status information includes the type and condition
of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing,
and break interrupt.
KK16C554 includes a programmable baud rate generator which is capable of dividing the timing reference clock input
by divisors of 1 to 216-1, and producing a 16x clock for driving the internal transmitter logic. Provisions are also
included to use this clock to drive the receiver logic.
KK16C554 has complete MODEM-control capability and an interrupt system that can be programmed to the user’s
requirements, minimizing the computing required to handle the communication links.
2. Features
z In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the
number of interrupts to CPU.
z Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
z Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial
data.
z Independently controlled transmit, receive, line status and data interrupts.
z Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 216-1 and
generate an internal 16X clock.
z Independent receiver clock input
z Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
z Fully programmable serial interface characteristics.
- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit
- 1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, KK16C554 checks only one stop bit, no matter
how many they are)
z False start bit detection
z Generates or Detects Line Break
z Internal diagnostic capabilities : Loop-back controls for communications link fault isolation.
z Full prioritized interrupt system controls
1
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KK16C554PL pdf, 数据表
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KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
LCR LCR LCR LCR LCR LCR LCR LCR
00000000
Word Length 0 0 = 5 Data Bits
Select
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
Stop Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6,7,8 Data Bits Selected
0 = Parity Disabled
Parity Enable 1 = Parity Enabled
0 = Odd Parity
Even Parity 1 = Even Parity
0 = Stick Parity Disabled
Stick Parity 1 = Stick Parity Enabled
Break Control 0 = Break Disabled
1 = Break Enabled
Divisor Latch 0 = Access Receiver Buffer
Access Bit 1 = Access Divisor Latches
Figure 1. Line Control Register
* Programmable Baud Generator
The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to 14.7456MHz and dividing it by any
divisor from 2 to 216-1. 4MHz is the highest clock input recommended when the divisor = 1. The output frequency of the baud generator is 16 x
baud [divisor # = (frequency input)/(baud rate X 16)]. Two 8-bit latches store the divisor in a 16-bit binary format. These Divisor Latches must be
loaded during initialization to ensure proper operation of the Baud Generator. (see Table 2.)
Table 2. Baud rates
This table provides decimal divisors to use with crystal frequencies of 1.8432MHz, 3.6864MHz, 7.3728MHz and 14.7456MHz. For baud rates
of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate is dependent on the frequency of the crystal. It is not
recommended using a divisor of zero.
Decimal divisor to generate 16x Clock
Desired baud rate
1.8432MHz
3.6864MHz
7.3728MHz
14.7456MHz
50
2304
4608
9216
18432
75
1536
3072
6144
12288
134.5
857
1714
3428
6856
150
768
1536
3072
6144
300
384
768
1536
3072
600 192 384 768 1536
1200 96 192 384 768
1800 64 128 256 512
2000 58 116 232 464
2400 48 96 192 384
3600 32 64 128 256
4800 24 48 96 192
7200 16 32 64 128
9600 12 24 48 96
19.2K
6
12 24 48
38.4K
3
6 12 24
57.6K
2
4
8 16
115.2K
1
2
4
8
230.4K
-
1
2
4
460.8K
-
-
1
2
921.6K
-
-
-
1
8
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KK16C554PL equivalent, schematic
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KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
7.5. Transmitter switching characteristics over recommended ranges of operating free-air temperature and
supply voltage (See Fig 3~5.)
tirs Delay time, INTxto TXDxat start
tsti Delay time, TXDxat start to INTx
tsi Delay time, IOW# high or low (WR THR) to INTx
tsxa Delay time, TXDxat start to TXRDY#
thr Propagation delay time, IOW#(WR THR)to INTx
tir Propagation delay time, IOR#(RD IIR)to INTx
twxi Propagation delay time, IOW#(WR THR)to TXRDY#
MIN MAX UNIT
8 24 RCLK cycles
8 8 RCLK cycles
16 32 RCLK cycles
8 RCLK cycles
35 ns
30 ns
50 ns
7.6. Receiver switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (Fig 6~9.)
tsint Delay time, stop bit to INTxor stop bit to RXRDY# or read RBR to set interrupt
trint Propagation delay time, Read RBR/LSR to INTx/LSR interrupt
trint Propagation delay time, IOR# RCLKto RXRDY#
MIN MAX UNIT
1 RCLK cycle
40 ns
40 ns
7.7. Modem control switching characteristics over recommended ranges of operating free-air temperature and
supply voltage (See Fig 10.)
tmdo Propagation delay time, IOW#(WR MCR)to RTSx#, DTRx#
tsim Propagation delay time, modem input CTSx#, DSRx#, and DCDx#↓↑ to INTx
trim Propagation delay time, IOR#(RD MSR)to interrupt
tsim Propagation delay time, Rix#to INTx#
MIN
MAX
50
30
35
30
단위
ns
ns
ns
ns
A[2:0]
CSx#
IOR#
IOW#
D[7:0]
VALID ADDRESS
t csr
t frc
t ar
t rd
t ra
t rcs
trc
trvd thz
VALID DATA
Fig 1. Read Cycle Timing
ACTIVE
16
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