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PDF ( 数据手册 , 数据表 ) ZL30112

零件编号 ZL30112
描述 SLIC/CODEC DPLL
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL30112 数据手册, 描述, 功能
ZL30112
SLIC/CODEC DPLL
Data Sheet
Features
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
www.datas1he9e.4t44u.cMomHz input
• Provides 2.048 MHz and 8.192 MHz output clocks
and an 8 kHz framing pulse
• Automatic entry and exit from freerun mode on
reference fail
• Provides DPLL lock and reference fail indication
• DPLL bandwidth of 29 Hz for all rates of input
references
• Less than 0.6 nsecpp intrinsic jitter on all output
clocks
• 20 MHz external master clock source: clock
oscillator or crystal
• Simple hardware control interface
November 2007
Ordering Information
ZL30112LDE1
32 Pin QFN* Tubes, Bake
& Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Synchronizer for POTS SLIC/CODEC
• Rate convert NTR 8 kHz or GPON physical
interface clock to TDM clock
Description
The ZL30112 SLIC/CODEC DPLL contains a digital
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30112 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
Reference
Monitor
State Machine
Master
Clock
REF_FAIL
LOCK
DPLL
Mode
Control
C2o
C8o
F8ko
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.







ZL30112 pdf, 数据表
4.0 Modes of Operation
ZL30112
Data Sheet
www.datasheet4u.com
RST
Normal
(locked)
REF_DIS=1
REF_DIS=0
freerun
REF_DIS=1
REF_DIS=0
TIE Correction
REF_DIS=1: Current selected reference disrupted (see Figure 3)
Figure 5 - Modes of Operation
Normal Mode
In Normal mode, the ZL30112 provides timing and frame synchronization signals which are synchronized to the
reference input (REF). The input reference signal may have a nominal frequency of 8 kHz, 2.048 MHz, 8.192 MHz,
or 19.44 MHz. The frequency of the reference inputs are automatically detected by the reference monitors.
Automatic Freerun Mode
Automatic freerun mode is typically used for short durations while system synchronization is temporarily disrupted.
In Automatic freerun mode, the ZL30112 provides timing and synchronization signals, which are not locked to an
external reference signal, but are based on the freerun accuracy of the external oscillator.
5.0 Measures of Performance
The following are some PLL performance indicators and their corresponding definitions.
5.1 Jitter Generation (Intrinsic Jitter)
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander
is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low
frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or
20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter
numbers, not cycle-to-cycle jitter.
5.2 Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
8
Zarlink Semiconductor Inc.







ZL30112 equivalent, schematic
ZL30112
Data Sheet
AC Electrical Characteristics* - Input to output timing for reference REF (see Figure 11).
Characteristics
Symbol
Min. Max.
1 8 kHz reference input to F8ko delay
2 2.048 MHz reference input to F8ko delay
www.datash3eet4u.c8om.192 MHz reference input to F8ko delay
4 19.44 MHz reference input to F8ko delay
tREF8kD
tREF2_F8kD
tREF8_F8kD
tREF19_F8kD
-0.3 2
-1.1 0.9
-0.6 0.8
-1.7 1
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Units
ns
ns
ns
ns
REF
tREF<xx>P
tREFW
tREFW
output clock with
the same frequency
as REF
F8ko
tREF<xx>D
tREF8D, tREF<xx>_F8kD
Figure 11 - Input to Output Timing
AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input
Characteristics
Sym. Min. Typ. Max.
1 Oscillator Tolerance
-32 +32
2 Duty cycle
40 60
3 Rise time
10
4 Fall time
10
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Units
ppm
%
ns
ns
Notes
16
Zarlink Semiconductor Inc.










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