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PDF ( 数据手册 , 数据表 ) IP1203PBF

零件编号 IP1203PBF
描述 Single Output Full Function Synchronous Buck Power Block
制造商 International Rectifier
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IP1203PBF 数据手册, 描述, 功能
PD- 97108
iP1203PbF
www.datasheet4u.com
Features
• 5.5V to 13.2V Input Voltage
• 0.8V to 8V Output Voltage
• 15A Maximum Load Capability
• 200-400kHz Nominal Switching Frequency
• Over Current Hiccup
• External Synchronization Capable
• Overvoltage Protection
• Over Temperature Protection
• Internal Features Minimize Layout Sensitivity
• Very Small Outline 9mm x 9mm x 2.3mm
Single Output Full Function
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
iP1203PbF Power Block
Description
The iP1203PbF is a fully optimized solution for medium current synchronous buck applications requiring up to
15A. It includes full function PWM control, with optimized power semiconductor chipsets and associated
passives, achieving high power density. Very few external components are required to create a complete
synchronous buck power supply.
iPOWIRtechnology offers designers an innovative space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers benefits
in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1203PbF Simplified Application Schematic
VIN
VIN OC
VCC_bypass
VSW
FB
FBS
SPGSOODiPiP11220033PbF
VOUT
Pin Number
(See Page 18) Pin Name
1, 23
VIN
Pin Description
Input voltage connection pins
2,3,4,5,7,17,20,21 PGND
Power Ground pins
6 VCC_bypass
PWM controller power supply pin. Internally generated.
Requires a 2.2µf external bypass capacitor
8
SS
Soft start pin. External capacitor provides soft start. Pulling soft start pin low
will disable the output. Cannot be cycled to unlatch OVP trip
9 CC
Output of the error amplifier
10 FB
Inverting input of the error amplifier
RT
SYNC
CC
VREF
11
12
13
14
15
PACKAGE
DESCRIPTION
iP1203PbF
iP1203TRPbF
INTERFACE
CONNECTION
LGA
LGA
PARTS PER
BAG
PARTS
PER
REEL
10 ---
--- 1000
16
T&R
ORIENTATION
Fig 26
18,19
22
24
8/11/06
FBs Output overvoltage sense pin.
RT
Switching frequency setting pin. For RT selection, refer to Fig.9 of the
datasheet
PGOOD
Power Good pin. Open collector, requires external pulll-up. If function not
needed, pin can be left floating
VREF
Non inverting input of the error amplifier (reference Voltage pin). Connect a
100pF cap from this pin to PGND.
SYNC
External Clock synchronization pin. Set free running frequency to 80% of
the SYNC frequency. When not in use, leave pin floating
OCSET
Output overcurrent trip threshold pin
VSW
VSWs
VINs
Output inductor connection pins
Test pad, for internal use, short to VSW
Test pad, for internal use, short to VIN







IP1203PBF pdf, 数据表
iP1203PbF
Example 2) Adjusting for SOA Temperature:
www.datasheet4uA.csosmuming TCASE = 110°C & TPCB = 90°C for both outputs
Output1 (Fig. 4) Normalized SOA Temperature for input voltage +0.7°C
(Fig. 5) Normalized SOA Temperature for output voltage -0.75°C
(Fig. 6) Normalized SOA Temperature for frequency +1.0°C
(Fig. 7) Normalized SOA Temperature for inductor value ≈ +2.0°C
TX axis intercept temp adjustment = +0.5°C - 0.75°C + 1.0°C +2.0°C +2.75°C
The following example shows how the SOA current is adjusted for a TX change of +2.75°C and output is in SOA
0
16
10 20 30 40 50 60 70 80 90 100 110 120
Case Temperature (ºC)
14
Unadjusted SOA curve
12 Adjusted SOA curve
10
8
6
VIN = 12V
4 VOUT = 1.5V
fSW = 300kHz
2 L=1.0uH
iPi1P210230P3bFSOSAOA
TX
0
0 10 20 30 40 50 60 70 80 90 100 110 120
PCB Temperature (ºC)
VSW
iPi1P210230P3 bF
FB
Iin Average
A
V Vin Average Cin
Vin DC
PIN= VINAverage x IINAverage
P = V Average xI Average
OUT OUT
OUT
PLoss = PIN - POUT
Iout Average
Lo Vout
A
Co
Iout
Averaging
Circuit
V Vout Average
Fig. 10: Power Loss Test Circuit
8 www.irf.com







IP1203PBF equivalent, schematic
iP1203PbF
The frequencies of the three poles and the two zeros
of the Type III compensation scheme are represented
www.dbaytatshheeetf4oul.lcoowming equations:
fp1= 0
(18)
f p2
=
2π
1
× R21
× C8
(19)
f
p3
=
2π
×
1
R20
× C7
(20)
f z1
=
2π
1
× R20
× C9
fz2
=
2π
1
× R2
× C8
(21)
(22)
7. Place the second pole fp2 at or near fesr of the out-
put capacitor Co and
equation (19). Make
determine
sure R21 <
the value
R2
10
of
R21
from
8. Use equation (24) to calculate R5.
R5 = R2 x
Vref
Vo - Vref
(24)
More than one iteration may be required to calculate
the values of the compensation components if cross-
over frequencies higher than the range specified in
step 1 are required (for higher bandwidths and faster
transient response performance). To ensure stability
a phase margin greater than 45° should be achieved.
Refer to AN-1043 for more detailed compensation
techniques using Transconductance Amplifiers.
The crossover frequency f0 for Type III compensa-
tion is represented by equation (23):
f0
1
= Vramp
×VIN
× R20
× C8
×
2π
1
× L0
× C0
(23)
Follow the steps below to determine the feedback
loop compensation component values:
1. Select a zero db crossover frequency f0 in the range
of 10% to 20% of the switching frequency fsw.
2. Select R20~ 10k
3. Place the first zero fz1 at 75% of the resonant fre-
quency fLC of the output filter.
Determine C9 from equation (21).
4. Place a third pole fP3 at or near the switching fre-
quency fSW.
Select C7 such that C7 <
C9
10
5. Calculate C8 from equation (23).
6. Place the second zero at 125% of the resonant
frequency fLC of the output filter. Calculate R2 using
equation (22).
16 www.irf.com










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