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PDF ( 数据手册 , 数据表 ) D784225GC

零件编号 D784225GC
描述 UPD784225GC
制造商 NEC
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D784225GC 数据手册, 描述, 功能
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784224, 784225, 784224Y, 784225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD784224 and 784225 are products of the µPD784225 Subseries in the 78K/IV Series. Besides a high-
speed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A
converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral
hardware.
The µPD784224Y and 784225Y are based on the µPD784225 Subseries with the addition of a multimaster-
supporting I2C bus interface.
Flash memory versions, the µPD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM
version with flash memory, and various development tools are also available.
The functions are explained in detail in the following user’s manuals. Be sure to read this manual when
designing your system.
µPD784225, 784225Y Subseries User’s Manual - Hardware : U12697E
78K/IV Series User’s Manual - Instruction
: U10905E
FEATURES
• I2C bus
• ROM correction
• Inherits peripheral functions of µPD780058Y
Subseries
• Minimum instruction execution time
160 ns (main system clock fXX = 12.5 MHz)
61 µs (subsystem clock fXT = 32.768 kHz)
• I/O port: 67 pins
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 4 units
• Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, multi-master supporting I2C
busNote): 1 channel
Note µPD784225Y Subseries only
• Standby function
HALT/STOP/IDLE mode
In power-saving mode: HALT/IDLE mode (with
subsystem clock)
• Clock division function
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Clock output function
fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
selectable
• Buzzer output function
fXX/210, fXX/211, fXX/212, fXX/213 selectable
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Supply voltage: VDD = 1.8 to 5.5 V
APPLICATION FIELD
Car audio, portable audio, telephones, etc.
Unless contextually excluded, references in this document to µPD784225 mean µPD784224, 784225, 784224Y,
and 784225Y.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Document No. U12376EJ1V0DS00 (1st edition)
Date Published May 2000 J CP(K)
Printed in Japan
The mark shows major revised points.
©
1997, 2000







D784225GC pdf, 数据表
µPD784224, 784225, 784224Y, 784225Y
2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND µPD780058Y SUBSERIES
Item
Series Name
µPD784225, 784225Y
Subseries
µPD784216Y Subseries µPD780058Y Subseries
CPU
16-bit CPU
8-bit CPU
Minimum
www.dataisnhsetreutc4tuio.cnom
execution time
With main system
clock selected
With subsystem
clock
160 ns (at 12.5 MHz)
61 µs (at 32.768 kHz)
400 ns (at 5.0 MHz)
122 µs (at 32.768 kHz)
Memory space
1 Mbytes
64 Kbytes
I/O port
Total
67 pins
86 pins
68 pins
CMOS input
8 pins
8 pins
2 pins
CMOS I/O
59 pins
72 pins
62 pins
N-ch open-drain I/O
6 pins
4 pins
Pins with
ancillary
functionNote 1
Pins with pull-up
resistor
LED direct drive
output
57 pins
16 pins
70 pins
22 pins
66 pins (flash memory
model: 62 pins)
12 pins
Medium-voltage pin
6 pins
4 pins
Timer/counter
• 16-bit timer/event counter
× 1 unit
• 8-bit timer/event counter
× 4 units
• 16-bit timer/event counter
× 1 unit
• 8-bit timer/event counter
× 6 units
• 16-bit timer/event counter
× 1 unit
• 8-bit timer/event counter
× 2 units
Serial interface
• UART/IOE (3-wire serial I/O) × 2 channels
• CSI (3-wire serial I/O, multi-master supporting I2C
busNote 2) × 1 channel
• UART (time-division transfer
function)/IOE (3-wire
serial I/O) × 2 channels
• CSI (3-wire serial I/O,
2-wire serial I/O,
I2C bus) × 1 channel
• CSI (3-wire serial I/O
with automatic
transmission/reception
function) × 1 channel
Interrupt
NMI pin
Provided
None
Macro service
Provided
None
Context switching Provided
None
Programmable priority 4 levels
2 levels
Standby function
• HALT/STOP/IDLE mode
• Power-saving mode: HALT/IDLE Mode
HALT/STOP mode
ROM correction
Provided
None
Provided
Package
• 80-pin plastic QFP
(14 × 14 mm)
• 80-pin plastic TQFP
(fine pitch) (12 × 12 mm)
• 100-pin plastic QFP
(fine pitch) (14 × 14 mm)
• 100-pin plastic QFP
(14 × 20 mm)
• 80-pin plastic QFP
(14 × 14 mm)
• 80-pin plastic TQFP
(fine pitch) (12 × 12 mm)
Notes 1. Pins with ancillary function are included in the I/O pins.
2. µPD784225Y and 784216Y Subseries only
8 Data Sheet U12376EJ1V0DS00







D784225GC equivalent, schematic
µPD784224, 784225, 784224Y, 784225Y
5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins
Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection
of unused pins.
For the circuit diagram of each type of I/O circuit, refer to Figure 5-1.
Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)
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Pin Name
I/O Circuit Type
I/O
Recommended Connections of Unused Pins
P00/INTP0
P01/INTP1
8-K I/O Input : Individually connected to VSS0 via resistor
Output: Open
P02/INTP2/NMI
P03/INTP3 to P05/INTP5
P10/ANI0 to P17/ANI7
9
Input Connected to VSS0 or VDD0
P20/RxD1/SI1
P21/TxD1/SO1
10-I
10-J
I/O Input : Individually connected to VSS0 via resistor
Output: Open
P22/ASCK1/SCK1
10-I
P23/PCL
10-J
P24/BUZ
P25/SDA0Note/SI0
10-I
P26/SO0
P27/SCL0Note/SCK0
10-J
10-I
P30/TO0 to P32/TO2
8-M
P33/TI1, P34/TI2
8-K
P35/TI00, P36/TI01
8-L
P37/EXA
8-M
P40/AD0 to P47/AD7
5-H
P50/A8 to P57/A15
P60/A16 to P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P70/RxD2/SI2
8-K
P71/TxD2/SO2
8-L
P72/ASCK2/SCK2
8-K
Note This function is available in µPD784255Y Subseries only.
Remark Because the circuit type numbers are standardized among the 78K Series products, they are not
sequential in some models (i.e., some circuits are not provided).
16 Data Sheet U12376EJ1V0DS00










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