DataSheet8.cn


PDF ( 数据手册 , 数据表 ) NT512D72S8PB0G

零件编号 NT512D72S8PB0G
描述 184 pin Unbuffered DDR DIMM
制造商 ETC
LOGO ETC LOGO 


1 Page

No Preview Available !

NT512D72S8PB0G 数据手册, 描述, 功能
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
512MB, 256MB and 128MB
PC3200, PC2700 and PC2100
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
www.daBtaassheedeto4nu.DcoDmR400/333/266 256M bit B Die device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 256M bit die B device,
organized as either 32Mbx8 or 16Mbx16
• Performance:
PC3200 PC2700 PC2100
Speed Sort
5T 6K 75B Unit
DIMM CAS Latency
3 2.5 2.5
fCK Clock Frequency
200 166 133 MHz
tCK Clock Cycle
5 6 7.5 ns
fDQ DQ Burst Frequency 400 333 266 MHz
• Intended for 133, 166 and 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = VDDQ = 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5, 3
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts
• SDRAMs are packaged in TSOP packages
• “Green” packaging – lead free
Description
NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,
NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM
Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.
NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8
TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,
NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.
NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,
organized as single rank using four 16Mx16 TSOP devices.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation
type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be
accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 2.2
Aug 3, 2004
Preliminary
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.







NT512D72S8PB0G pdf, 数据表
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
2 Ranks, 18 devices (ECC), 32Mx8 DDR SDRAMs
S1
www.datasheetS40u.com
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D0
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D1
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D8
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D9
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D10
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D11
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D12
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D17
BA0-BA1
A0-A13
RAS
CAS
CKE0
CKE1
WE
BA0-BA1 : SDRAMs D0-D17
A0-A13 : SDRAMs D0-D17
RAS : SDRAMs D0-D17
CAS : SDRAMs D0-D17
CKE : SDRAMs D0-D8
CKE : SDRAMs D9-D17
WE : SDRAMs D0-D17
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D16
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
SPD
D0-D8
D0-D8
D0-D8
Strap: see Note 4
* Clock Wiring
Clock Input SDRAMs
*CK0/CK0
6 SDRAMs
*CK1/CK1
6 SDRAMs
*CK2/CK2
6 SDRAMs
* Wire per Clock Loading Table/
Wiring Diagrams
Serial PD
SCL
WP
A0 A1 A2
SDA
SA0 SA1 SA2
Notes :
1. DQ-to-I/O wring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
REV 2.2
Aug 3, 2004
Preliminary
8
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.







NT512D72S8PB0G equivalent, schematic
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
VIN, VOUT
www.datasheeVt4INu.com
Voltage on I/O pins relative to VSS
Voltage on Input relative to VSS
-0.5 to VDDQ +0.5
-0.5 to +3.6
V
V
VDD Voltage on VDD supply relative to VSS
-0.5 to +3.6
V
VDDQ
Voltage on VDDQ supply relative to VSS
-0.5 to +3.6
V
TA Operating Temperature (Ambient)
0 to +70
°C
TSTG Storage Temperature (Plastic)
-55 to +150
°C
PD Power Dissipation (per device component)
1W
IOUT Short Circuit Output Current
50 mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics and Operating Conditions
TA= 0°C ~ 70°C; VDDQ= VDD= 2.5V±0.2V(PC2100,PC2700); TA= 0°C ~ 70°C; VDDQ= VDD= 2.6V±0.1V(PC3200)
Symbol
VDD
VDDQ
VSS, VSSQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VID (DC)
II
Parameter
Supply Voltage
PC2100, PC2700
PC3200
I/O Supply Voltage
PC2100, PC2700
PC3200
Supply Voltage, I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and CK Inputs
Input Differential Voltage, CK and CK Inputs
Input Leakage Current
Any input 0V VIN VDD;
All other pins not under test = 0V
Min
2.3
2.5
2.3
2.5
0
0.49 x VDDQ
VREF – 0.04
VREF + 0.15
-0.3
-0.3
0.30
Max
2.7
2.7
0
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
-10 10
Units
V
V
V
V
V
V
V
V
V
µA
Notes
1
1
1, 2
1, 3
1
1
1
1, 4
1
Output Leakage Current
IOZ
DQs are disabled; 0V Vout VDDQ
-10 10 µA 1
Output High Current
IOH
(VOUT = VDDQ -0.373V, min VREF, min VTT)
-16.8
- mA 1
Output Low Current
IOL
(VOUT = 0.373, max VREF, max VTT)
16.8 - mA 1
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,
and must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
REV 2.2
Aug 3, 2004
Preliminary
16
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.










页数 28 页
下载[ NT512D72S8PB0G.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
NT512D72S8PB0G184 pin Unbuffered DDR DIMMETC
ETC

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap