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PDF ( 数据手册 , 数据表 ) 92CD54IF

零件编号 92CD54IF
描述 TMP92CD54IF
制造商 Toshiba Semiconductor
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92CD54IF 数据手册, 描述, 功能
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CMOS 32-bit Micro-controller
TMP92CD54IF
TMP92CD54I
1. Outline and Device Characteristics
TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling
equipment which processes mass data.
TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and
various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package.
Device characteristics are as follows:
(1) CPU : 32-bit CPU(900/H1 CPU)
Compatible with TLCS-900,900/L,900/L1,900/H,900/H2’s instruction code
16Mbytes of linear address space
General-purpose register and register banks
Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case)
Minimum instruction execution time : 50ns(at 20MHz)
Internal data bus : 32-bit
(2) Internal memory
Internal RAM : 32K-byte
Internal ROM : 512K-byte Mask ROM
92CD54I-1
2006-01-27







92CD54IF pdf, 数据表
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TMP92CD54I
Pin name
PN1
SO0
SDA0
PN2
SI0
SCL0
PN3
SCK1
A12
PN4
SO1
SDA1
A13
PN5
SI1
SCL1
A14
PN6
SO2
SDA2
A15
Pin
number
60th
62nd
64th
65th
66th
67th
NMI
39th
INT0
37th
Number
of pins
1
1
1
1
1
1
1
1
In/Out
Function
in/out
out
in/out
in/out
in
in/out
in/out
in/out
out
in/out
out
in/out
out
in/out
in
in/out
out
in/out
out
in
Port N1: I/O port.
SBI channel 0: Output data input/output at SIO mode
SBI channel 0: Data input/output at I²C mode
Port N2: I/O port.
SBI channel 0: Input data at SIO mode
SBI channel 0: Clock input/output at I²C mode
Port N3: I/O port.
SBI channel 1: Clock input/output at SIO mode
Address: Address bus 12.
Port N4: I/O port.
SBI channel 1: Output data at SIO mode
SBI channel 1: Data input/output at I²C mode
Address: Address bus 13.
Port N5: I/O port.
SBI channel 1: Input data at SIO mode
SBI channel 1: Clock input/output at I²C mode
Address: Address bus 14
Port N6: I/O port.
SBI channel 2: Output data at SIO mode
SBI channel 2: data input output at I2C mode
Address: Address bus 15.
Non-maskable interrupt: Interrupt request pin with programmable falling or both
falling and rising edge.
NMI
Interrupt request pin 0: Interrupt request pin with programmable level or
in rising-edge.
INT0
AM0,1
TEST0,1
CLK
X1/X2
80th, 78th
76th, 71st
77th
74th, 72nd
XT1/XT2 70th, 69th
RESET
79th
VREFH
4th
VREFL
3rd
ADVCC
2nd
ADVSS
1st
DVCC5
15th, 40th,
50th,61st,75th
DVCC3 36th,68th,86th
DVSS
13th,38th,51st,
63rd,73rd,88th
REGOUT 49th
REGEN
52nd
2
2
1
2
2
1
1
1
1
1
5
3
6
1
1
in Address Mode selection: Connect AM0 pin to L, AM1 pins to H.
in Test mode pins: Should be set to L.
out Programmable clock output (with pull-up register)
in/out
in/out
in
Oscillator connecting pins
Low frequency oscillator connecting pins. Crystal or ceramic resonator is connected.
RC oscillation is also possible
Reset: Initializes LSI (with pull-up register).
in AD reference voltage high
in AD reference voltage low
- Power supply pin for AD converter (+5V): Connect ADVCC pin to 5V power supply.
- GND pin for AD converter: Connect ADVSS pin to GND (0V).
- Power supply pins (+5V): Connect all DVCC5 pins to 5V power supply.
- Power supply pins (+3.3V): Connect all DVCC3 pins to REGOUT pin.
- GND: Connect all DVSS pins to GND (0V).
out Regulator output 3.3V: Connect capacitor to stabilize the regulator output.
in Regulator enable pin: Should be set to H or OPEN (with pull-up register).
92CD54I-8
2006-01-27







92CD54IF equivalent, schematic
www.datasheet4u.com
TMP92CD54I
Table 3.3.3 Source of Halt state clearance and Halt clearance operation
Status of Received Interrupt
Interrupt Enabled
Interrupt Disabled
(interrupt level) (interrupt mask) (interrupt level) < (interrupt mask)
Halt mode
NMI
INTWDT
INT0
INT0 [MASK]
INT1 to 7
INTT0 to 7
INTTR8 to B
INTTO8, INTTOA
INTRX0 to 1, TX0 to 1
INTCR0, INTCT0, INTCG0
INTSEM0, E0, R0, T0
INTSBE0, S0, E1, S1, E2, S2
INTAD
All the above-mentioned interrupts [MASK]
INTRTC
INTRTC [MASK]
RESET
Idle2



{









×

{

Idle1

×

{
×
×
×
×
×
×
×
×
×
×

{

Idle3
*1
×
*1 *2
{*1 *2
×
×
×
×
×
×
×
×
×
×
*1
{*1

Stop
*1
×
*1 *2
{*1 *2
×
×
×
×
×
×
×
×
×
×
×
×

Idle2
{
{
×
×
×
×
×
×
×
×
×
×
{
{

Idle1
{
{
×
×
×
×
×
×
×
×
×
×
{
{

Idle3
{*1 *2
{*1 *2
×
×
×
×
×
×
×
×
×
×
{*1
{*1

Stop
{*1 *2
{*1 *2
×
×
×
×
×
×
×
×
×
×
×
×

: After clearing the Halt mode, CPU starts interrupt processing. (RESET initializes the microcont.)
{: After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT
instruction.
×: Cannot be used to clear the Halt mode.
: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level.
There is not this combination type.
*1: The Halt mode is cleared when the warm-up time has elapsed.
*2: Any WUINT interrupt (WUINT0 to WUINT7) generate an INT0 interrupt.
Note 1: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status,
hold level H until starting interrupt processing. If level L is set before holding level H, interrupt
processing is not correctly started.
Note 2: When the external interrupts INT5 to INT7 are used during Idle2 Mode, set to 1 for TRUN8<I2T8>
and TRUNA<I2TA>.
(Example - clearing Idle1 Mode)
An INT0 interrupt clears the Halt state when the device is in Idle1 Mode.
Address
8203H
8206H
8209H
820BH
820EH
INT0
LD
LD
EI
LD
HALT
(IIMC), 00H
(INTE0AD), 06H
5
(CLKMOD), 80H
820FH
LD XX, XX
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets interrupt level to 5 for CPU.
; Sets Halt mode to Idle1 Mode.
; Halts CPU.
INT0 interrupt routine
RETI
92CD54I-16
2006-01-27










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