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PDF ( 数据手册 , 数据表 ) C8051F000

零件编号 C8051F000
描述 (C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family
制造商 Silicon Laboratories
LOGO Silicon Laboratories LOGO 


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C8051F000 数据手册, 描述, 功能
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mixed-Signal 32KB ISP FLASH MCU Family
a
ANALOG PERIPHERALS
- SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
±1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
- Two 12-bit DACs
www.DataSheet4U.c-om Two Analog Comparators
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
- Voltage Reference
2.4V; 15 ppm/°C
Available on External Pin
- Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
- Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low Cost Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- 21 Vectored Interrupt Sources
MEMORY
- 256 Bytes Internal Data RAM (F000/01/02/10/11/12)
- 2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
- 32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
- 4 Byte-Wide Port I/O; All are 5V tolerant
- Hardware SMBusTM (I2CTM Compatible), SPITM, and UART
Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
- Four General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer
- Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC,C, or Clock
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................2.7V to 3.6V
- Typical Operating Current: 12.5mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
SAR
ADC
12-Bit
DAC
12-Bit
DAC
VREF
+
+-
-
VOLTAGE
COMPARATORS
DIGITAL I/O
PCA
SMBus
SPI Bus
UART
Timer 0
Timer 1
Timer 2
Timer 3
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
ISP FLASH
CLOCK
CIRCUIT
JTAG
DEBUG
CIRCUITRY
256/2304 B
21
SANITY
SRAM INTERRUPTS CONTROL
Rev. 1.7 11/03
Copyright © 2003 by Silicon Laboratories







C8051F000 pdf, 数据表
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1. SYSTEM OVERVIEW
The C8051F000 family are fully integrated mixed-signal System on a Chip MCUs with a true 12-bit multi-channel
ADC (F000/01/02/05/06/07), or a true 10-bit multi-channel ADC (F010/11/12/15/16/17). See the Product Selection
Guide in Table 1.1 for a quick reference of each MCUs’ feature set. Each has a programmable gain pre-amplifier,
two 12-bit DACs, two voltage comparators (except for the F002/07/12/17, which have one), a voltage reference,
and an 8051-compatible microcontroller core with 32kbytes of FLASH memory. There are also I2C/SMBus,
UART, and SPI serial interfaces implemented in hardware (not “bit-banged” in user software) as well as a
Programmable Counter/Timer Array (PCA) with five capture/compare modules. There are also 4 general-purpose
16-bit timers and 4 byte-wide general-purpose digital Port I/O. The C8051F000/01/02/10/11/12 have 256 bytes of
RAM and execute up to 20MIPS, while the C8051F005/06/07/15/16/17 have 2304 bytes of RAM and execute up to
25MIPS.
www.DataSheet4U.cWomith an on-board VDD monitor, WDT, and clock oscillator, the MCUs are truly stand-alone System-on-a-Chip
solutions. Each MCU effectively configures and manages the analog and digital peripherals. The FLASH memory
can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the
8051 firmware. Each MCU can also individually shut down any or all of the peripherals to conserve power.
On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit debug using
the production MCU installed in the final application. This debug system supports inspection and modification of
memory and registers, setting breakpoints, watchpoints, single stepping, and run and halt commands. All analog
and digital peripherals are fully functional when using JTAG debug.
Each MCU is specified for 2.7V-to-3.6V operation over the industrial temperature range (-45C to +85C). The Port
I/Os, /RST, and JTAG pins are tolerant for input signals up to 5V. The C8051F000/05/10/15 are available in the
64-pin TQFP (see block diagram in Figure 1.1). The C8051F001/06/11/16 are available in the 48-pin TQFP (see
block diagram in Figure 1.2). The C8051F002/07/12/17 are available in the 32-pin LQFP (see block diagram in
Figure 1.3).
Table 1.1. Product Selection Guide
C8051F000 20 32k 256 √ √ √ 4 32 12 100 8 √ √ 12 2 2 64TQFP
C8051F001 20 32k 256 √ √ √ 4 16 12 100 8 √ √ 12 2 2 48TQFP
C8051F002 20 32k 256 √ √ √ 4 8 12 100 4 √ √ 12 2 1 32LQFP
C8051F005 25 32k 2304 √ √ √ 4 32 12 100 8 √ √ 12 2 2 64TQFP
C8051F006 25 32k 2304 √ √ √ 4 16 12 100 8 √ √ 12 2 2 48TQFP
C8051F007 25 32k 2304 √ √ √ 4 8 12 100 4 √ √ 12 2 1 32LQFP
C8051F010 20 32k 256 √ √ √ 4 32 10 100 8 √ √ 12 2 2 64TQFP
C8051F011 20 32k 256 √ √ √ 4 16 10 100 8 √ √ 12 2 2 48TQFP
C8051F012 20 32k 256 √ √ √ 4 8 10 100 4 √ √ 12 2 1 32LQFP
C8051F015 25 32k 2304 √ √ √ 4 32 10 100 8 √ √ 12 2 2 64TQFP
C8051F016 25 32k 2304 √ √ √ 4 16 10 100 8 √ √ 12 2 2 48TQFP
C8051F017 25 32k 2304 √ √ √ 4 8 10 100 4 √ √ 12 2 1 32LQFP
Rev. 1.7
8







C8051F000 equivalent, schematic
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.4. Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. All four ports are pinned out on the
F000/05/10/15. Ports 0 and 1 are pinned out on the F001/06/11/16, and only Port 0 is pinned out on the
F002/07/12/17. The Ports not pinned out are still available for software use as general purpose registers. The Port
I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the “weak pull-ups” which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low power
applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network
that allows mapping of internal digital system resources to Port I/O pins on P0, P1, and P2. (See Figure 1.8.)
Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported.
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The on-board counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar
Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for his particular application.
Figure 1.8. Digital Crossbar Diagram
Highest
Priority
Lowest
Priority
Port
Latches
SMBus
SPI
UART
PCA
Comptr.
Outputs
T0, T1,
T2
SYSCLK
CNVSTR
2
4
2
6
2
6
8
P0 (P0.0-P0.7)
8
P1 (P1.0-P1.7)
8
P2 (P2.0-P2.7)
8
P3 (P3.0-P3.7)
XBR0, XBR1,
XBR2 Registers
PRT0CF, PRT1CF,
PRT2CF Registers
Priority
Decoder
Digital
Crossbar
8
8
P0
I/O
Cells
P1
I/O
Cells
8
P2
I/O
Cells
PRT3CF
Register
P3
I/O
Cells
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
P2.0
P2.7
Lowest
Priority
P3.0
P3.7
Rev. 1.7
16










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