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PDF ( 数据手册 , 数据表 ) TMP1942XBG

零件编号 TMP1942XBG
描述 32bit TX System RISC
制造商 Toshiba Semiconductor
LOGO Toshiba Semiconductor LOGO 


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TMP1942XBG 数据手册, 描述, 功能
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32bit TX System RISC
TX19 family
TMP1942CYUE
TMP1942CZUE/XBG
Rev1.0 March 29, 2007







TMP1942XBG pdf, 数据表
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TX1942CY/CZ
Figure 2.1.2 shows pin assignment for the 177-pin model of the TMP1942.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
E1 E2 E3 E4
E12 E13 E14 E15
F1 F2 F3 F4
F12 F13 F14 F15
G1 G2 G3 G4
G12 G13 G14 G15
H1 H2 H3 H4
H12 H13 H14 H15
J1 J2 J3 J4
J12 J13 J14 J15
K1 K2 K3 K4
K12 K13 K14 K15
L1 L2 L3 L4
L12 L13 L14 L15
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Figure 2.1.2 177-Pin CSP Pin Assignment
TMP1942CY/CZ-7







TMP1942XBG equivalent, schematic
TMP1942CY/CZ
3. Functional Description
This section describes the functions and basic operation of each individual circuit block in the TMP1942 series
devices.
3.1 Processor Core
The TX1942 contains a high-performance 32-bit processor core (the TX19 processor core). For details of
the operation of the processor core, refer to TX19 Family Architecture”.
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Functions unique to the TMP1942, which are not explained in TX19 Family Architecture”, are described
below.
Recommended power-on sequence:
In powering up this device, it is recommended that the DVCC3 be turned on first.
At power-on, the pull-up resistors and input & output buffers pull-down resistors attached to
the I/O ports of the 5V supply domain may rail become unstable or a through current may pass
through the port until the DVCC3 has stabilized, when an injection order is not kept.
3.1.1
Reset Operation
To reset the TMP1942, RESET must be input Low (at 0) for at least 12 system clock cycles while the
power supply voltage is within the rated operating range and the internal high-frequency oscillator is
oscillating stably. (With the device operating at 32 MHz, this period is equal to 3 μs if the PLL is being
used and 6 μs if the PLL is not being used.) After a reset the PLL-multiplied clock is specified by the
setting of the PLLOFF pin and the clock gear is initialized to 1/8 mode.
To reset the TMP1942, RESET must be asserted for at least 12 system clock periods after the power
supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 3 μs at 32
MHz when the on-chip PLL is utilized, and 6μs otherwise. After a reset, either the PLL-multiplied clock
or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected
clock is geared down to 1/8 for internal operation.
The following occurs as a result of a reset:
The System control coprocessor (CP0) registers within the TX19 core processor are initialized.
For details, refer to the Architecture manual.
The Reset exception is taken. Program control is transferred to the exception handler at a
predefined address. This predefined location is called an exception vector, which directly
indicates the start of the actual exception handler routine. The Reset exception is always
vectored to virtual address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt
exception).
All on-chip I/O peripheral registers are initialized.
All port pins, including those multiplexed with on-chip peripheral functions, are configured as
either general-purpose inputs or general-purpose outputs.
TMP1942CY/CZ-15










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