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PDF ( 数据手册 , 数据表 ) TB1308FG

零件编号 TB1308FG
描述 (TB1305FG / TB1308FG) Sync Separation and H/V Frequency Counter IC
制造商 Toshiba Semiconductor
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TB1308FG 数据手册, 描述, 功能
TB1305FG, TB1308FG
TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB1305FG,TB1308FG
Component SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1305FG and TB1308FG include a component SW block, a
prefilter for AD conversion, sync separation and H/V format
detectors for TV component video signals.
The TB1305FG and TB1308FG contribute to reduction in the
proportion of PCB occupied by LCR filters and to the simplification of
www.DataSheet4U.comdesigns on analog interfaces.
The TB1305FG and TB1308FG are equipped with an I2CBUS
interface through which various functions can be controlled.
P-QFP48-1014-0.80
Weight: 0.83 g (typ.)
Features
COMPONENT BLOCK
Component video input: TB1305FG 2 channels, TB1308FG 3 channels; RGB available
Component video output
Gain switching: 0dB / +6dB
Bandwidth filter: prefilter for ADC; 4.2 to 31MHz variable)
SYNC SEPARATION BLOCK
Supports 525/60i/60p, 625/50i/50p, 750/50p/60p, 1125/50i/60i/50p/60p, 1250/50i,
VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60
HD/VD input: 2 channels; positive and negative input acceptable
HD/VD output: positive and negative output selectable
Masking pseudo-sync for copyguard signal
OTHERS
Line detector for D-pin (2 channels)
Horizontal and vertical frequency counter
Format detection circuit for input signal
Automatic sync process switching mode
Lineup
Part No.
TB1305FG
TB1308FG
Number of component video inputs
2
3
1 2007-07-11







TB1308FG pdf, 数据表
TB1305FG, TB1308FG
Register Name
SYNC SW
www.DataSheet4U.com
HV FREQ
HV-SEP
VGA-SEP
PS MASK
Function
Preset Value
Switches sync input.
Sync input to HD/VD-OUT and to SYNC-OUT is selected.
HD OUT (pin 30) VD OUT (pin 29)
SYNC OUT (pin 28)
000 SYNC1 (pin 8)
001 SYNC2 (pin 16)
010 SYNC3 (pin 38: TB1308FG only)
011 Not available
100 HD1 (pin 24)
VD1 (pin 23)
SYNC1 (pin 8)
101 HD2 (pin 26)
VD2 (pin 25)
SYNC2 (pin 16)
110 HD1 (pin 24)
VD1 (pin 23)
SYNC3
(pin 38 : TB1308FG only)
111 HD2 (pin 26)
VD2 (pin 25)
SYNC3
(pin 38: TB1308FG only)
SYNC1
(000)
NOTE: SYNC3 of the data 010, 110, 111 is not available for the TB1305FG.
Input format setting
Set the horizontal and vertical mode according to the format that is input.
0000: 15.625 kHz, 50 Hz (625i) 0001: 15.75 kHz, 60 Hz (525i)
0010: 31.25 kHz, 50 Hz (625p) 0011: 31.5 kHz, 60 Hz (525p, VGA@60Hz)
0100: 28.125 kHz, 50 Hz (1125/50i)0101: 33.75 kHz, 60 Hz (1125/60i)
0110: 37.5 kHz, 50 Hz (750/50p) 0111: 45 kHz, 60 Hz (750/60p, XGA@60Hz) 15.625 kHz, 50 Hz
1000: 31.25 kHz, 50 Hz (1250i)
(0000)
1001: 37.9 kHz, 60 Hz (SVGA@60Hz)
1010: 64 kHz, 60 Hz (1125/60p, SXGA@60Hz)
1011: 75 kHz, 60 Hz (UXGA@60Hz)
1100: 56.25 kHz, 50 Hz (1125/50p)
1101 ~ 1111: Not available
Switches the separation level.
The H/V sync separation level to SYNC-IN (pins 8, 16, 38) is switched.
0: LOW
1: HIGH
Remark: The separation level is changed according to the ratio of negative sync
width per H period and the connected resistance.
LOW
(0)
Switches the separation level.
The H/V sync separation level to SYNC-IN (pins 8, 16, 38) is switched for PC
signals.
Normal
0: Normal (component video)
1: VGA
(0)
Remark: The separation level is changed according to the ratio of negative sync
width per H period and the connected resistance.
Switches the mask mode for pseudo-sync.
Pseudo-syncs in lines are removed.
OFF
0: OFF (V-BLK period only)
1: ON (all lines)
(0)
NOTE: Set PS MASK = 1 (ON) for except “Sync on G”.
8 2007-07-11







TB1308FG equivalent, schematic
TB1305FG, TB1308FG
www.DataSheet4U.com
200
180
160
140
120
100
80
60
40
20
0
0
f0 SW = Low, fc HALF = ON
f0 SW = High, fc HALF = ON
f0 SW = Low
f0 SW = High
20 40 60 80 100 120
BANDWIDTH data [Dec]
Figure. Typical delay-time (group delay @ 1MHz) characteristics of prefilter due to
BANDWIDTH data.
Note on 1125/50p/60p input
When 1125/50p and/or 60p signal are input, GAIN = 0(0dB) and FILPASS = 0(ON) are recommended due to the
performance of the slew rate and cutoff frequency of the TB1305FG and TB1308FG circuits. A gain amplifier and/or a
prefilter for 1125/50p/60p should be added as external circuits, if necessary.
Note on video output pins
To conduct the video signal from the TB1305FG or TB1308FG to the following circuits, a buffer such as the one in
the application circuits is required due to the drive capability of the TB1305FG and TB1308FG being insufficient,
especially for high-frequency components.
The DC levels of the video output vary according to I2CBUS functions, the APL of the input and temperature
drift.Therefore, the DC levels should be re-clamped in connected circuits such as AD converters.
Recommended crystal oscillator
When a connected crystal oscillator is used for the XO, the following oscillation specifications are required.
Oscillation frequency (fundamental): 3.579545 MHz (for NTSC decoding)
Frequency tolerance: +/- 50 ppm
External CW input into crystal oscillator pin
Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 21 through a
capacitor as below.
The specifications required for CW input are as follows.
Input frequency (fundamental): 3.579545 MHz +/- 50 ppm
Input amplitude: 1.0 Vp-p +/- 0.5 Vp-p
16 2007-07-11










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