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PDF ( 数据手册 , 数据表 ) CY14B104N

零件编号 CY14B104N
描述 4-Mbit (512K x 8/256K x 16) nvSRAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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CY14B104N 数据手册, 描述, 功能
PRELIMINARY
CY14B104L, CY14B104N
4-Mbit (512K x 8/256K x 16) nvSRAM
Features
15 ns, 25 ns, and 45 ns access times
Internally organized as 512K x 8 (CY14B104L) or 256K x 16
(CY14B104N)
Hands off automatic STORE on power down with only a small
capacitor
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STORE to
QuantumTrap®
nonvolatile
elements
initiated
by
software, device pin or AutoStore® on power down
RECALL to SRAM initiated by software or power up
Infinite read, write, and recall cycles
8 mA typical ICC at 200 ns cycle time
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20%, –10% operation
Commercial and industrial temperatures
FBGA and TSOP - II packages
RoHS compliance
Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 512K words of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Logic Block Diagram
VCC VCAP
[1]
Address A0 - A18
CE
OE
WE
BHE
BLE
CY14B104L
CY14B104N
[1]
DQ0 - DQ7
HSB
VSS
Note
1. Address A0 - A18 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-07102 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 02, 2008
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CY14B104N pdf, 数据表
PRELIMINARY
CY14B104L, CY14B104N
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [9]
Parameter
Description
ΘJA Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
48-FBGA 44-TSOP II 54-TSOP II Unit
TBD
TBD
TBD °C/W
TBD
TBD
TBD °C/W
AC Test Loads
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3.0V
OUTPUT
30 pF
577Ω
R1
R2
789Ω
3.0V
OUTPUT
5 pF
577Ω
R1
for tri-state specs
R2
789Ω
Document #: 001-07102 Rev. *F
Page 8 of 22
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CY14B104N equivalent, schematic
PRELIMINARY
CY14B104L, CY14B104N
Ordering Information (continued)
Speed
(ns)
Ordering Code
45 CY14B104L-ZS45XCT
CY14B104L-ZS45XIT
CY14B104L-ZS45XI
CY14B104L-BA45XCT
CY14B104L-BA45XIT
CY14B104L-BA45XI
www.DataSheet4U.com CY14B104L-ZSP45XCT
CY14B104L-ZSP45XIT
CY14B104L-ZSP45XI
CY14B104N-ZS45XCT
CY14B104N-ZS45XIT
CY14B104N-ZS45XI
CY14B104N-BA45XCT
CY14B104N-BA45XIT
CY14B104N-BA45XI
CY14B104N-ZSP45XCT
CY14B104N-ZSP45XIT
CY14B104N-ZSP45XI
Package
Diagram
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
Package Type
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 001-07102 Rev. *F
Page 16 of 22
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