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PDF ( 数据手册 , 数据表 ) K9F1G08R0A

零件编号 K9F1G08R0A
描述 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9F1G08R0A 数据手册, 描述, 功能
K9F1G08R0A
K9F1G08U0A K9K2G08U1A
Document Title
128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0
0.1
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1. Initial issue
1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 23~26)
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added Addressing method for program operation
0.2 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
0.3 1. PKG(TSOP1, WSOP1) Dimension Change
0.4 1. Technical note is changed
2. Notes of AC timing characteristics are added
3. The description of Copy-back program is changed
4. Voltage range is changed
-1.7V~1.95V -> 1.65V~1.95V
5. Note2 of Command Sets is added
0.5 1. CE access time : 23ns->35ns (p.11)
0.6 1. The value of tREA for 3.3V device is changed.(18ns->20ns)
2. EDO mode is added.
0.7 1. The flow chart to creat the initial invalid block table is cahnged.
Draft Date Remark
Aug. 24. 2003 Advance
Jan. 27. 2004 Preliminary
Apr. 23. 2004 Preliminary
May. 19. 2004 Preliminary
Jan. 21. 2005 Preliminary
Feb. 14. 2005 Preliminary
May. 24. 2005
May 6. 2005
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1







K9F1G08R0A pdf, 数据表
K9F1G08R0A
K9F1G08U0A K9K2G08U1A
FLASH MEMORY
Product Introduction
The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 col-
umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con-
nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells
that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND
structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read opera-
tions are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 sep-
arately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08X0A.
The K9F1G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
www.DataSheet4U.ecxoammple, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 128M byte physical space
requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-
ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-
mand register. Table 1 defines the specific commands of the K9F1G08X0A.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
Read
Read for Copy Back
Read ID
Reset
Page Program
Cache Program*2
Copy-Back Program
Block Erase
Random Data Input*1
Random Data Output*1
Read Status
1st. Cycle
00h
00h
90h
FFh
80h
80h
85h
60h
85h
05h
70h
2nd. Cycle
30h
35h
-
-
10h
15h
10h
D0h
-
E0h
Acceptable Command during Busy
O
O
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Cache program and Copy-Back program are supported only with 3.3V device.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
8







K9F1G08R0A equivalent, schematic
K9F1G08R0A
K9F1G08U0A K9K2G08U1A
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE
CE don’t-care
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WE
ALE
I/Ox
80h Address(4Cycles)
Data Input
Data Input
10h
tCS tCH
tCEA
CE CE
tWP
WE
RE
I/O0~7
tREA
out
Figure 5. Read Operation with CE don’t-care.
CLE
CE
RE
ALE
R/B
WE
I/Ox
tR
00h
Address(4Cycle)
30h
16
CE don’t-care
Data Output(serial access)










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