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PDF ( 数据手册 , 数据表 ) 46R22

零件编号 46R22
描述 HT46R22
制造商 Holtek Semiconductor
LOGO Holtek Semiconductor LOGO 


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46R22 数据手册, 描述, 功能
HT46R22/HT46C22
8-Bit A/D Type MCU
www.DataSheet4U.com
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 4.5V~5.5V
· 19 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with over-
flow interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 2048´14 program memory ROM
· 64´8 data memory RAM
· Supports PFD for sound generation
· HALT function and wake-up feature reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· 6-level subroutine nesting
· 8 channels 9-bit resolution (8-bit accuracy) A/D con-
verter
· 1-channel (6+2)/(7+1)-bit PWM output shared with
two I/O lines
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· Low voltage reset function
· I2C BUS (slave mode)
· 24-pin SKDIP/SOP package
General Description
The device is an 8-bit high performance RISC-like
microcontroller designed for multiple I/O product appli-
cations. It is particularly suitable for use in products
such as washing machine controllers and home appli-
ances. A HALT feature is included to reduce power con-
sumption.
I2C is a trademark of Philips Semiconductors
Rev. 1.10
1
October 2, 2002







46R22 pdf, 数据表
HT46R22/HT46C22
www.DataSheet4U.com
Stack register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 6 return ad-
dresses are stored).
Data memory - RAM
The data memory is designed with 92´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(64´8). Most are read/write, but some are read only.
The special function registers include the indirect ad-
dressing register (00H), timer/event counter register
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer register (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register 0 (INTC0;
0BH), PWM data register (PWM;1AH), the I2C BUS
slave address register (HADR;20H), the I2C BUS con-
trol register (HCR;21H), the I2C BUS status register
(HSR;22H), the I2C BUS data register (HDR;23H), the
A/D result lower-order byte register (ADRL;24H), the
A/D result higher-order byte register (ADRH;25H), the
A/D control register (ADCR;26H), the A/D clock setting
register (ACSR;27H), I/O registers (PA;12H, PB;14H,
PC;16H, PD;18H) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PDC;19H). The remaining space
before the 40H is reserved for future expanded usage
and reading these locations will get ²00H². The general
purpose data memory, addressed from 40H to 7FH, is
used for data and control information under instruction
commands.
0 0 H In d ir e c t A d d r e s s in g R e g is te r
01H M P
02H
03H
04H
05H A C C
06H P C L
07H TB LP
08H TB LH
09H
0A H S TA TU S
0 B H IN T C 0
0C H
S p e c ia l P u r p o s e
D ATA M EM O R Y
0D H TM R
0E H TM R C
0.H
10H
11H
12H P A
13H P A C
14H P B
15H P B C
16H P C
17H P C C
18H P D
19H P D C
1A H P W M
1B H
:U nused
R e a d a s "0 0 "
1C H
1D H
1 E H IN T C 1
1.H
20H H A D R
21H H C R
22H H S R
23H H D R
24H A D R L
25H A D R H
26H A D C R
27H A C S R
28H
3.H
4 0 H G e n e ra l P u rp o s e
D ATA M EM O R Y
(6 4 B y te s )
7.H
RAM mapping
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
Rev. 1.10
8 October 2, 2002







46R22 equivalent, schematic
HT46R22/HT46C22
www.DataSheet4U.com
lected, the PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the
PA3 to remain at ²0². The I/O functions of PA3 are
shown below.
I/O I/P O/P I/P
Mode (Normal) (Normal) (PFD)
O/P
(PFD)
PA3
Logical
Input
Logical
Output
Logical
PFD
Input (Timer on)
Note: The PFD frequency is the timer/event counter
overflow frequency divided by 2.
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0. If the PWM function is en-
abled, the PWM signal will appear on PD0 (if PD0 is op-
erating in output mode). Writing ²1² to PD0 data register
will enable the PWM output function and writing ²0² will
force the PD0 to remain at ²0². The I/O functions of PD0
is as shown.
I/O I/P O/P I/P
Mode (Normal) (Normal) (PWM)
O/P
(PWM)
PD0
Logical
Input
Logical
Output
Logical
Input
PWM
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
PWM
The microcontroller provides 1 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0. The PWM channel has its data registers denoted
as PWM(1AH). The frequency source of the PWM coun-
ter comes from fSYS. The PWM registers is a 8-bit regis-
ter. The waveforms of PWM outputs are as shown.
Once the PD0 is selected as the PWM outputs and the
output function of PD0 is enabled (PDC.0=²0²), writing 1
to PD0 data register will enable the PWM output func-
tion and writing ²0² will force the PD0 to stay at ²0².
fS Y S /2
[P W M ] = 1 0 0
PW M
2 5 /6 4
[P W M ] = 1 0 1
PW M
2 6 /6 4
[P W M ] = 1 0 2
PW M
2 6 /6 4
[P W M ] = 1 0 3
PW M
2 6 /6 4
P W M m o d u la tio n p e r io d : 6 4 /fS Y S
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
P W M c y c le : 2 5 6 /fS Y S
(6+2) PWM mode
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
fS Y S /2
[P W M ] = 1 0 0
PW M
5 0 /1 2 8
[P W M ] = 1 0 1
PW M
5 1 /1 2 8
[P W M ] = 1 0 2
PW M
5 1 /1 2 8
[P W M ] = 1 0 3
PW M
5 2 /1 2 8
P W M m o d u la tio n p e r io d : 1 2 8 /fS Y S
Rev. 1.10
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
P W M c y c le : 2 5 6 /fS Y S
(7+1) PWM mode
16
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
October 2, 2002










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