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PDF ( 数据手册 , 数据表 ) QG80331M550

零件编号 QG80331M550
描述 I/O Processor
制造商 Intel
LOGO Intel LOGO 


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QG80331M550 数据手册, 描述, 功能
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Intel® 80331 I/O Processor
Specification Update
April 2006
The Intel® 80331 I/O Processor may contain design defects or errors known as errata that may
cause the product to deviate from published specifications. Current characterized errata are doc-
umented in this specification update.
Order Number: 273930-021US







QG80331M550 pdf, 数据表
Intel® 80331 I/O Processor
Preface
Preface
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This document is an update to the specifications contained in the Affected Documents/Related
Documents table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system manufacturers and
software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification update and are
no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents/Related Documents
Title
Intel® 80331 I/O Processor Developer’s Manual
Intel® 80331 I/O Processor Datasheet
Intel® 80331 I/O Processor Design Guide
Order
273942
273943
273823
Nomenclature
Errata are design defects or errors. These may cause the Intel® 80331 I/O Processor1 behavior to
deviate from published specifications. Hardware and software designed to be used with any given
stepping must assume that all errata documented for that stepping are present on all devices.
Specification Changes are modifications to the current published specifications. These changes
will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These will be incorporated in any new release of the specification.
Note:
Errata remain in the specification update throughout the product’s lifecycle, or until a particular
stepping is no longer commercially available. Under these circumstances, errata removed from the
specification update are archived and available upon request. Specification changes, specification
clarifications and documentation changes are removed from the specification update when the
appropriate changes are made to the appropriate product specification or user documentation
(datasheets, manuals, etc.).
1. ARM* architecture compliant.
8 Specification Update







QG80331M550 equivalent, schematic
Intel® 80331 I/O Processor
Summary Table of Changes
Documentation Changes
No.
1
2
3
4
5
6
www.DataSheet4U.com 7
8
9
10
11
12
13
14
15
16
17
Document Revision
273942-002
273942-002
273942-002
273942-002
273942-002
273942-002
273942-002
273942-002
273942-002
273823-001
273943-001
273942-002
273942-002
273942-002
273823-002
273943-001
273942-002
Page
61
61
61
61
61
61
62
62
63
66
66
66
67
67
67
67
67
Status
Documentation Changes
Doc Table 236 shows incorrect description for tWDL field
Doc Processor Device ID should be removed
Doc Core Performance Monitoring Unit (CPMON) section is incorrect
Doc UART FIFO Occupancy Register is read only
Doc Refresh Frequency Register table is incorrect
Doc PBI interrupt should be removed
Doc ARB_EN has been de-featured
Doc Flash wait state information is incorrect
Doc SDCR0 and SDCR1 register updates
Doc Power sequence timing
Doc Updated Peripheral Bus Interface (PBI) timings
Doc ATU PM_CAP[5] text must be updated
Doc WDTCR also affected by TMR1[3]
Doc Split Completion Message clarification
Doc Figure 49 in Design Guide shows incorrect trace length
Doc Wrong Voltage Values in Table 21
Doc SBR1 Programming When Bank 1 is Unpopulated
16 Specification Update










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