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PDF ( 数据手册 , 数据表 ) AK2345

零件编号 AK2345
描述 FRS CTCSS Encoder/Decoder
制造商 Asahi Kasei Microsystems
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AK2345 数据手册, 描述, 功能
ASAHI KASEI
[AK2345]
AK2345
FRS CTCSS Encoder/Decoder
Features
1. CTCSS (Continuous Tone Controlled Squelch System) Encoder/Decoder.
2. Programmable for up to 50 CTCSS frequencies.
3. Integrated CTCSS signal elimination filter.
4. Built-in Adder TX CTCSS/CDCSS and voice signal.
5. Built-in high speed CTCSS Decoder.
6. Conform to CDCSS. (Continuous Digital Controlled Squelch System)
7. Integrated voice signal circuits such as a limiter, splatter filter, etc.
8. Built-in (3.6864 MHz or 4.194304 MHz) oscillator circuit with crystal oscillator.
9. Control register controlled via serial interface.
10. CMOS Process low voltage operation. (1.8V…5.5V)
11. Compact plastic package is used. (24 pin VSOP)
(Page 25)
Description
The AK2345 is an IC which supports CTCSS (Continuous Tone Controlled Squelch System),
compatible with the TIA/EIA-603 standard.
A single CTCSS may be selected from among 50 different frequencies within a range of from
67 to 254.1 Hz. By sending that CTCSS simultaneously with the voice signal during
transmission, and by setting the audio circuit so that it operates only when a CTCSS of that
frequency is detected, it is possible to have multiple communications on the same radio
frequency.
TX has a built-in Adder CTCSS and voice signal, and RX has a built-in high-speed CTCSS
Decoder respectively.
Voice signal filters, a limiter, op-amp, and other circuits are integrated, making it possible to
configure a radio base band unit, especially FRS from a single chip.
Pin assignment
TXIN1
TXIN2
TXINO
MOD
MODIN
SPOUT
RXOUT
VDD
XIN
XOUT
STB
SDATA/DCS
1
2
3
4
5
6
7
8
9
10
11
12
24 RXTONE
23 RXIN
22 RXINO
21 AGNDIN
20 AGND
19 LIMLV
18 LIMBS
17 DREF
16 TXTONE
15 VSS
14 DETOUT
13 SCLK
C0041-E-03
-1-
2006/09







AK2345 pdf, 数据表
ASAHI KASEI
[AK2345]
Digital Characteristics
1) DC Characteristics
Parameter
Pin Symbol Min. Typ. Max. Units
High level input voltage
(1) VIH 70%VD+
Low level input voltage
(1) VIL
High level input current VIH=VD+ (1)
IIH
Low level input current VIL=0V
(1) IIL
-10
Low level output voltage IOL=0.8mA (2)
VOL
(1) SDATA/DCS, SCLK, STB
(2) DETOUT
30%VD+
10
0.3
V
V
uA
uA
V
2) AC Characteristics
Parameter
Symbol Min.
Typ.
Max.
Master Clock Frequency CKSL=”1”
CKSL=”0”
fclk
3.6864
4.194304
Serial data input timing
Clock pulse width 1
ta 500
Clock pulse width 2
tb 500
SDATA set up time
tc 100
SDATA hold time
td 100
STROBE Set up time
te 100
STROBE pulse width
tf 100
STROBE dehold time
tg 100
digital input rising time
th
250
digital input falling time
ti
250
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
SDATA/DCS
ta tb
tc td
SA1
SA0
SD5
STB
te
SD0
CDCSS Data
tf tg
th ti
0.9DVDD
0.1DVDD
Serial Data Input
Note) CDCSS code is acceptable after STB has fallen. Specified period of time is Tg.
While CDCSS is transmitting, please set SCLK pin is fixed to high level and STB pin to
low.
C0041-E-03
-8-
2006/09







AK2345 equivalent, schematic
ASAHI KASEI
3) Setting of the master clock frequency and AMP4 Gain
Address
SA1 SA0
10
SD5
GA3
SD4
CKSL
Data
SD3 SD2
TXON
GA2
SD1
GA1
Data name
CKSL
TXON
Master clock
frequency
TXIN2 pin control
Function
”1”: 3.6864MHz
“0”: 4.194304MHz
“1”: OFF (Mute)
“0”: ON
Data name
Function
GA3
GA2
GA1
GA0 AMP4 Gain (dB)
1000
0.0
0000
1.5
1001
3.0
0001
4.5
1010
6.0
0010
7.5
1011
9.0
0011
10.5
1100
12.0
0100
13.5
1101
15.0
0101
16.5
1110
18.0
0110
19.5
1111
21.0
0111
22.5
[AK2345]
SD0
GA0
C0041-E-03
- 16 -
2006/09










页数 27 页
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