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PDF ( 数据手册 , 数据表 ) W682388

零件编号 W682388
描述 CODEC Layout Guideline
制造商 Winbond
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W682388 数据手册, 描述, 功能
W682388 Layout Guideline Rev 1.3
-
AN-CS006a
W682388 Pro-X™ CODEC Layout Guideline
www.DataSheet4U.com
1. W682388 Layout Considerations
The Winbond W682388 Pro-XCODEC family is an excellent solution for short loop telephony
applications. Place the components carefully to insure best performance. This document outlines critical
component layout issues. Use it together with the W682388 data sheet and other supporting Pro-X
application notes.
The W682388 will exhibit high-quality low-noise performance with the appropriate layout design. Pins
52–61 are sensitive current input pins that are susceptible to induced noise. Keep traces between these
pins and their respective components (C7, C8, C10, C11, R13–16, and R18–27) to a minimum length. Do
not route any digital traces near these sensitive traces.
Place the line compensation capacitors, C5, C8, C9, and C12, near their respective TIP and RING output
pins. Place a 0.1 µF ceramic decoupling capacitor as close as possible to each VDD and VBAT power
supply input pin. These are Pin 49 (VDD1), Pin 64 (VDD2), Pin 41 (VDD3), Pin 8 (VDD4), Pin 27 (VDD5)
and Pin 26 (VDDL). Replace the 0.1 µF capacitors at VDD1 and VDD2 with 10 µF ceramic capacitors for
additional noise performance. Refer to the Figure 3 for an example of this layout.
There are two external Tip and Ring capacitors for each channel. They are connected to CT1 (Pin 39), CR1
(Pin 38), CT2 (Pin 10), and CR2 (Pin 11). The capacitor is a 10 µF ceramic (low leakage) capacitor. It is
connected to 3.3V. Route the capacitors directly to the appropriate VDD pin. For example, the CT1 and
CR1 capacitors connect directly to their respective pins. Their shared 3.3V connection is routed directly to
VDD1 before connecting to the main 3.3V supply. The situation is the same for CT2 and CR2, which must
terminate at VDD2.
The AFE transistors QR3/QT3 (SOT-223) and QR1/QT1 (SOT-89) should have exposed copper pads to
help reduce the thermal resistance of these components. The amount of copper used for the heat sink in
combination with the surface area of the PCB will improve the heat dissipation of the transistor package.
One way to increase the copper area when board space is limited is to connect the pad used for the heat
sink by using multiple layers. A top and bottom side can be used with multiple vias connecting them
together. The optimal copper area to heat sink a SOT-223 is 1 sq inch. This approach is similar to heat
sinking used for the QFN package. (Refer to Section 4 on QFN grounding)
Place the resistors for IREF (Pin 13) and the transconductance amplifiers (Pins 3,5,44 and 46) as close as
possible to the part to minimize the trace length. These resistors are R29, R30 and R31.
If more than two layers are used for the overall board circuit, separate analog and digital trace layers may
enhance performance. Digital signals are best applied to a dedicated layer. The ideal approach is to
separate digital layers from analog layers by a power/ground plane.
AN-CS006a_W682388 PCB Layout.doc
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W682388 pdf, 数据表
W682388 Layout Guideline Rev 1.3
6. VERSION HISTORY
VERSION
1.1
1.2
www.DataSheet4U.com
1.3
DATE
PAGE
DESCRIPTION
March 21,
2006
Initial revision
April 17,
2006
1,4,5,7 Modified per new layout and schematic annotation.
June 21, 1,2,3,7,8 Added paragraph on AFE layout and heat sinking. Changed a
2006
few words for clarity. Corrected typos.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own
risk and agree to fully indemnify Winbond for any damages resulting from such improper use or
sales.
The information contained in this document may be subject to change without
notice. It is the responsibility of the customer to check the Winbond USA website
(www.winbond-usa.com) periodically for the latest version of this document, and
any Errata Sheets that may be generated between document revisions.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
2727 North First Street, San Jose,
27F, 2299 Yan An W. Rd. Shanghai,
CA 95134, U.S.A.
200336 China
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 1-408-5441798
FAX: 86-21-62365998
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
AN-CS006a_W682388 PCB Layout.doc
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