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PDF ( 数据手册 , 数据表 ) W681360

零件编号 W681360
描述 3V SINGLE-CHANNEL 13-BIT LINEAR VOICE-BAND CODEC
制造商 Winbond
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W681360 数据手册, 描述, 功能
W681360
www.DataSheet4U.com
3V SINGLE-CHANNEL 13-BIT LINEAR VOICE-BAND CODEC
Data Sheet
Publication Release Date: September 2005
- 1 - Revision A.2







W681360 pdf, 数据表
W681360
7. FUNCTIONAL DESCRIPTION
W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation.
The CODEC block diagram in Section 3 illustrates the main components of the W681360. The chip
consists of a PCM interface, which can process long and short frame sync formats. The pre-scaler of
the chip provides the internal clock signals and synchronizes the CODEC sample rate with the
external frame sync frequency. The power conditioning block provides the internal power supply for
the digital and the analog section, while the voltage reference block provides a precision analog
ground voltage for the analog signal processing.
www.DataSheet4U.comThe calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog
Converter (DAC) is referenced to μ-Law with the same bit voltage weighing about the zero crossing,
resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based
on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600.
VAG
+-
-+
13
DATA
Receive
13 bit linear
DAC
13
DATA
Transmit
13 bit linear
ADC
fC = 3400 Hz
Smoothing
Filter a
High Pass
Bypass
Smoothing
Filter b
fC = 200 Hz
High Pass
Filter
fC = 3400 Hz
Anti-Aliasing
Filter a
Anti-Aliasing
Filter b
Buffer1
Av=1
-
+
PAO+
PAO-
PAI
RO-
AO
AI-
AI+
FIGURE 7.1: THE W681360 SIGNAL PATH
7.1. Transmit Path
The first stage of the A-to-D path of the CODEC is an analog input operational
amplifier with externally configurable gain settings. A differential analog input may be
applied to the Inputs AI+ and AI-. Alternately the input amplifier may be powered
down and a single-ended input signal can be applied to either the AO pin or the AI-
pin. The input amplifier can be powered down by connecting the AI+ pin to either VDD
or VSS which also determines whether AO or AI+ is selected as input according to
Publication Release Date: September 2005
- 8 - Revision A.2







W681360 equivalent, schematic
W681360
SYMBOL
1/TFS
TFSL
1/TBCK
TBCKH
TBCKL
TFTRH
TFTRS
www.DataSheet4U.com
TFTFH
TFDTD
TBDTD
THID
TFRRH
TFRRS
TFRFH
TDRS
TDRH
TABLE 8.1: LONG FRAME SYNC PCM TIMING PARAMETERS
DESCRIPTION
FST, FSR Frequency
FST / FSR Minimum LOW Width 1
BCLKT, BCLKR Frequency 1
BCLKT, BCLKR HIGH Pulse Width
BCLKT, BCLKR LOW Pulse Width
BCLKT Falling Edge to FST Rising
Edge Hold Time
FST Rising Edge to BCLKT Falling
edge Setup Time
BCLKT Falling Edge to FST Falling
Edge Hold Time
The later of BCLKT rising edge, or FST
rising edge to first valid PCMT Bit Delay
Time
BCLKT Rising Edge to Valid PCMT
Delay Time
Delay Time from the Later of FST
Falling Edge, or
BCLKT Falling Edge of last PCMT Bit to
PCMT Output High Impedance
BCLKR Falling Edge to FSR Rising
Edge Hold Time
FSR Rising Edge to BCLKR Falling
edge Setup Time
BCLKR Falling Edge to FSR Falling
Edge Hold Time
Valid PCMR to BCLKR Falling Edge
Setup Time
PCMR Hold Time from BCLKR Falling
Edge
MIN
---
TBCK
256
50
50
20
80
50
---
---
10
20
80
50
1
50
TYP
8
---
---
---
---
---
---
---
MAX
---
4800
---
---
---
---
---
60
--- 60
--- 60
--- ---
--- ---
--- ---
--- ---
--- ---
UNIT
kHz
sec
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 TFSL must be at least TBCK
- 16 -
Publication Release Date: September 2005
Revision A.2










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