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PDF ( 数据手册 , 数据表 ) H8S2145B

零件编号 H8S2145B
描述 16-Bit Single-Chip Microcomputer
制造商 Renesas Technology
LOGO Renesas Technology LOGO 


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H8S2145B 数据手册, 描述, 功能
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
www.DataSheet4U.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003







H8S2145B pdf, 数据表
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 27,
List of Registers.
Rules:
Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation: Binary is B’xxxx, hexadecimal is H’xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: [[[[
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachisemiconductor.com/
H8S/2140B Series manuals:
Manual Title
www.DHa8taSS/2h1e40eBt4SUe.rcieosmHardware Manual
H8S/2600 Series, H8S/2000 Series Programming Manual
ADE No.
This manual
ADE-602-083
User's manuals for development tools:
Manual Title
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
H8S, H8/300 Series Simulator/Debugger User's Manual
H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging
Interface Tutorial
Hitachi Embedded Workshop User's Manual
ADE No.
ADE-702-247
ADE-702-282
ADE-702-231
ADE-702-201
Rev. 2.0, 08/02, page vi of xxxviii







H8S2145B equivalent, schematic
11.7.2 Conflict between FRC Write and Increment ........................................................262
11.7.3 Conflict between OCR Write and Compare-Match .............................................262
11.7.4 Switching of Internal Clock and FRC Operation .................................................264
11.7.5 Module Stop Mode Setting ..................................................................................266
Section 12 8-Bit Timer (TMR) ......................................................................... 267
12.1 Features .............................................................................................................................267
12.2 Input/Output Pins ..............................................................................................................270
12.3 Register Descriptions ........................................................................................................270
12.3.1 Timer Counter (TCNT) ........................................................................................271
12.3.2 Time Constant Register A (TCORA) ...................................................................271
12.3.3 Time Constant Register B (TCORB) ...................................................................271
12.3.4 Timer Control Register (TCR) .............................................................................272
12.3.5 Timer Control/Status Register (TCSR) ................................................................275
12.3.6 Input Capture Register (TICR).............................................................................281
12.3.7 Time Constant Register (TCORC) .......................................................................281
12.3.8 Input Capture Registers R and F (TICRR, TICRF)..............................................281
12.3.9 Timer Input Select Register (TISR) .....................................................................282
12.4 Operation...........................................................................................................................282
12.4.1 Pulse Output .........................................................................................................282
12.5 Operation Timing ..............................................................................................................283
www.DataSh1e2e.5t.41U.TcCoNmT Count Timing............................................................................................283
12.5.2 Timing of CMFA and CMFB Setting at Compare-Match ...................................284
12.5.3 Timing of Timer Output at Compare-Match ........................................................284
12.5.4 Timing of Counter Clear at Compare-Match .......................................................285
12.5.5 TCNT External Reset Timing ..............................................................................285
12.5.6 Timing of Overflow Flag (OVF) Setting..............................................................286
12.6 Operation with Cascaded Connection ...............................................................................286
12.6.1 16-Bit Count Mode ..............................................................................................286
12.6.2 Compare-Match Count Mode...............................................................................287
12.7 Input Capture Operation....................................................................................................287
12.8 Interrupt Sources ...............................................................................................................290
12.9 Usage Notes.......................................................................................................................291
12.9.1 Conflict between TCNT Write and Clear.............................................................291
12.9.2 Conflict between TCNT Write and Increment .....................................................292
12.9.3 Conflict between TCOR Write and Compare-Match ...........................................293
12.9.4 Conflict between Compare-Matches A and B......................................................294
12.9.5 Switching of Internal Clocks and TCNT Operation.............................................294
12.9.6 Mode Setting with Cascaded Connection ............................................................296
12.9.7 Module Stop Mode Setting ..................................................................................296
Section 13 Timer Connection............................................................................ 297
13.1 Features .............................................................................................................................297
Rev. 2.0, 08/02, page xiv of xxxviii










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