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PDF ( 数据手册 , 数据表 ) 82545EM

零件编号 82545EM
描述 Gigabit Ethernet Controller
制造商 Intel
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82545EM 数据手册, 描述, 功能
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82545EM Gigabit Ethernet Controller
Specification Update
June 6, 2006
The 82545EM Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate
from published specifications. Current characterized errata are documented in this Specification Update.
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82545EM pdf, 数据表
82545EM GIGABIT ETHENET CONTROLLER SPECIFICATION UPDATE
SUMMARY TABLE OF CHANGES
The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply
to the listed 82545EM steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the
other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations:
CODES USED IN SUMMARY TABLES
X:
Doc:
Fix:
Fixed:
NoFix:
(No mark) or (Blank Box):
Shaded:
Erratum, Specification Change or Clarification that applies to this stepping.
Document change or update that will be implemented.
This erratum is intended to be fixed in a future stepping of the component.
This erratum has been previously fixed.
There are no plans to fix this erratum.
This erratum is fixed in listed stepping or specification change does not apply to listed stepping.
This item is either new or modified from the previous version of the document.
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82545EM equivalent, schematic
82545EM GIGABIT ETHENET CONTROLLER SPECIFICATION UPDATE
12. Bus Initialization with Some Chipsets
Problem:
Implication:
www.DataSheet4U.cWomorkaround:
Status:
Upon initialization, the 82545EM controller samples the REQ64#, DEVSEL#, STOP# and TRDY# signals on the
rising (inactive) edge of RST#. If REQ64# is sampled low (asserted), then the controller starts up with a 64-bit
bus width. The values sampled on the other pins denote the PCI-X initialization pattern.
The PCI-X Addendum to the PCI Local Bus Specification calls for 0 ns minimum input hold time on these
signals. However, the 82545EM controller requires 1 ns input hold time.
If the signals do not have sufficient hold time, the 82545EM/82545EB controller could power up with incorrect
bus width (64 versus 32 bits) or mode (PCI/PCI-X 66/PCI-X 100/PCI-X 133). However, Intel has not observed
this problem in an actual system based on the 82545EM controller.
The problem cannot occur in systems based on the P64H2 PCI-X bridge because it drives the signals with a full
clock of hold time past the rising edge of RST#. Intel expects other contemporary bridges and chipsets to
perform the same way. The problem may be encountered in some systems based on legacy bridges and
chipsets.
Other loads on the PCI/PCI-X bus may affect the severity of the problem.
For LAN on motherboard designs, verify that the system bridge will deliver a full clock of hold time. If the
problem is encountered on an add-in board, try moving the board to a connector on another bus segment.
Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.
13. SMBALRT# Output Driven in ASF Mode
Problem:
Implication:
Workaround:
Status:
The SMBALRT# output signal has an additional function as a PCI_POWER_GOOD input in ASF mode
operation. However, the controller does not disable the SMBALRT# open drain output and contention between
the external PCI_POWER_GOOD signal and the internal SMBALRT# signal can result.
The Ethernet controller drives SMBALRT# low during communication between the ASF controller and the main
LAN controller logic. Depending on the drive strength of the external PCI_POWER_GOOD signal (or the value
of a pull-up resistor attached to the ball), the ASF controller may not observe PCI_POWER_GOOD asserted.
If PCI_POWER_GOOD cannot be observed following “OS Hang” event detection, the ASF controller may fail to
observe reset on the PCI bus, continuing to perform remote control operations such as EEPROM reloads.
Drive the PCI_POWER_GOOD input from a low impedance source (25 ohms or less).
Intel resolved this erratum in the A1 stepping of the 82545EM Gigabit Ethernet Controller.
14. ASF Lockup upon Resetting MAC
Problem:
Implication:
Workaround:
Status:
The ASF logic has a handshake problem at the expiration of its watchdog timer. When the ASF block attempts
to reset the MAC, an ASF lockup can occur.
The watchdog reset manageability function will not be available.
Intel has workaround ASF software and modified EEPROM settings to accompany the workaround. The
workaround disables MAC resets by the ASF logic (EEPROM Word 23h, Bit 2) and enables the ASF logic to
request ARP packets following the watchdog event.
Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.
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