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PDF ( 数据手册 , 数据表 ) ST62E28C

零件编号 ST62E28C
描述 8-BIT MCUs
制造商 STMicroelectronics
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ST62E28C 数据手册, 描述, 功能
ST62T28C/E28C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
www.DataSheet4Us.co-m40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s User Programmable Options
s 20 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 12 analog inputs
s 8-bit Asynchronous Peripheral Interface
(UART)
s 8-bit Synchronous Peripheral Interface (SPI)
s On-chip Clock oscill ator can be driven by
Quartz Crystal, Ceramic resonator or RC
network
s Oscillator Safe Guard
s Low Voltage Detector for safe Reset
s One external Non-Maskable Interrupt
s ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T28C
ST62E28C
OTP
(Bytes)
7948
EPROM
(Bytes)
-
7948
I/O Pins
20
20
November 1999
PDIP28
PS028
SS0P28
CDIP28W
(See end of Datasheet for Ordering Information)
Rev. 2.8
1/84
1







ST62E28C pdf, 数据表
ST62T28C/E28C
MEMORY MAP (Cont’d)
Table 1. ST62E28C/T28C Program Memory Map
ROM Page
Page 0
Page 1
“STATIC”
www.DataSheet4U.com
Page 2
Page 3
Device Address
0000h-007Fh
0080h-07FFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFB h
0FFCh-0FFDh
0FFEh-0FFFh
0000h-000Fh
0010h-07FFh
0000h-000Fh
0010h-07FFh
Description
Reserved
User ROM
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Reserved
User ROM
Reserved
User ROM
Note: OTP/EPROM devices can be programmed
with the development tools available from STMicro-
electronics (ST62E3X-EPB or ST623X-KIT).
1.3.2.1 Program ROM Page Register (PRPR)
The PRPR register can be addressed like a RAM
location in the Data Space at the address CAh;
nevertheless it is a write only register that cannot
be accessed with single-bit operations. This regis-
ter is used to select the 2-Kbyte ROM bank of the
Program Space that will be addressed. The
number of the page has to be loaded in the PRPR
register. Refer to the Program Space description
for additional information concerning the use of
this register. The PRPR register is not modified
when an interrupt or a subroutine occurs.
Care is required when handling the PRPR register
as it is write only. For this reason, it is not allowed
to change the PRPR contents while executing in-
terrupt service routine, as the service routine
cannot save and then restore its previous content.
This operation may be necessary if common rou-
tines and interrupt service routines take more than
2K bytes; in this case it could be necessary to di-
vide the interrupt service routine into a (minor) part
in the static page (start and end) and to a second
(major) part in one of the dynamic pages. If it is im-
possible to avoid the writing of this register in inter-
rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRPR it must write also
to the image register. The image register must be
written before PRPR, so if an interrupt occurs be-
tween the two instructions the PRPR is not af-
fected.
Program ROM Page Register (PRPR)
Address: CAh — Write Only
70
- - - - - - PRPR1 PRPR0
Bits 2-7= Not used.
Bit 5-0 = PRPR1-PRPR0: Program ROM Select.
These two bits select the corresponding page to
be addressed in the lower part of the 4K program
address space as specified in Table 2.
This register is undefined on Reset. Neither read
nor single bit instructions may be used to address
this register.
Table 2. 6Kbytes Program ROM Page Register
Coding
PRPR1
X
0
0
1
1
PRPR0
X
0
1
0
1
PC bit 11 Memory Page
1 Static Page (Page 1)
0 Page 0
0 Page 1 (Static Page)
0 Page 2
0 Page 3
1.3.2.2 Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the Program memory contents.
Returned parts with a protection set can therefore
not be accepted.
8/84
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ST62E28C equivalent, schematic
ST62T28C/E28C
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by re-
setting the OSCOFF bit of the A/D Converter Con-
trol Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
the software instruction at fLFAO clock frequency.
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
www.DataSheet4Um.coamin purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
This oscillator is available when the OSG ENA-
BLED option is selected. In this case, it automati-
cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provid-
ed, main oscillator switched off...).
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura-
cy is decreased, since the internal frequency is be-
low 1MHz.
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there-
fore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor starts.
ADCR
Address: 0D1h — Read/Write
70
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR
7 6 5 4 3 OFF 1 0
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register. These bits are not used.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
3.1.3 Oscillator Safe Guard
The Oscillator Safe Guard (OSG) affords drastical-
ly increased operational integrity in ST62xx devic-
es. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Os-
cillator (LFAO), used to ensure minimum process-
ing in case of main oscillator failure, to offer re-
duced power consumption or to provide a fixed fre-
quency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera-
tion even if the power supply should drop.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
2). In all cases, when the OSG is active, the maxi-
mum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent. This re-
lationship is illustrated in Figure 5.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscilla-
tor starts operating after the first missing edge of
the main oscillator (see Figure 3).
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequen-
cy with OSG enabled.
Note. The OSG should be used wherever possible
as it provides maximum safety. Care must be tak-
en, however, as it can increase power consump-
tion and reduce the maximum operating frequency
to fOSG.
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accu-
rate.
For precise timing measurements, it is not recom-
mended to use the OSG and it should not be ena-
bled in applications that use the SPI or the UART.
It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).
16/84
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