DataSheet8.cn


PDF ( 数据手册 , 数据表 ) 72SD3232

零件编号 72SD3232
描述 1 Gbit SDRAM 32-Meg X 32-Bit X 4-Banks
制造商 Maxwell Technologies
LOGO Maxwell Technologies LOGO 


1 Page

No Preview Available !

72SD3232 数据手册, 描述, 功能
72SD3232
1 Gbit SDRAM
32-Meg X 32-Bit X 4-Banks
www.DataSheet4U.com
Logic Diagram (One Amplifier)
FEATURES:
DESCRIPTION:
• 1 Gigabit ( 32-Meg X 32-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space
radiation
• Total Dose Hardness:
>100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
SELTH > 85 MeV/mg/cm2 @ 25°C
• JEDEC Standard 3.3V Power Supply
• Clock Frequency: 100 MHz Operation
• Operating tremperature: -55 to +125°C
• Auto Refresh
• Single pulsed RAS
• 2 Burst Sequence variations
Sequential (BL =1/2/4/8)
Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Power Down and Clock Suspend Modes
• LVTTL Compatible Inputs and Outputs
• Package: 72-Pin RAD-Stack Package
Maxwell Technologies’ Synchronous Dynamic Random
Access Memory (SDRAM) is ideally suited for space
applications requiring high performance computing and
high density memory storage. As microprocessors
increase in speed and demand for higher density mem-
ory escalates, SDRAM has proven to be the ultimate
solution by providing bit-counts up to 1 Gigabits and
speeds up to 100 Megahertz. SDRAMs represent a sig-
nificant advantage in memory technology over traditional
SRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation,
the ability to interleave between banks masking pre-
charge time, and the ability to randomly change column
address during each clock cycle.
Maxwell Technologies’ patented RAD-PAK® packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
for a lifetime in orbit or space mission. In a typical GEO
orbit, RAD-PAK® provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with
screening up to Maxwell Technologies self-defined Class
K.
02.04.05 Rev 3
All data sheets are subject to change without notice 1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2005 Maxwell Technologies
All rights reserved.







72SD3232 pdf, 数据表
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
72SD3232
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins:
COMMAND
SYMBOL
N-1
N
CS
RAS CAS
WE
BA0/
BA1
A10
A0 TO
A12
Ignore command
DESL
H
x
H
x
x
x
x
x
x
No Operation
NOP H x L H H H x x x
Column Address and READ
H
x
L
H
L
H
V
L
V
Read command
w w w . D a t a SRehadewiethtau4toU-pr.e-c o mREAD A H x L H L H V H V
charge
Column Address and WRIT
H
x
L
H
L
L
V
L
V
write command
Write with auto-pre- WRIT A H x L H L L V H V
charge
Row address strobe ACTV
H
x
L LHH V
V
V
and bank active
Precharge select
bank
PRE H x L L H L V L x
Precharge all banks PALL
H
x
L LHL
x
H
x
Refresh
REF/ H L L L L H x x x
SELF
Mode register set
MRS H
x
LLLL
V
V
V
Note: H: VIH L: VIL x VIH or VIL V: Valid address input
Ignore command (DESL): When this command is set (CS = High), the SDRAM ignores command input at
the clock. However, the internal status is held.
No Operation (NOP): This command is not an execution command. However, the internal operations
continue.
Column address strobe and read command (READ): This command starts a read operation. In addition,
the start address of a burst read is determined by the column address (AY0 to AY9) and the bank select
address (BS). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge (READ A): This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4, or 8.
02.04.05 Rev 3
All data sheets are subject to change without notice 8
©2005 Maxwell Technologies
All rights reserved.







72SD3232 equivalent, schematic
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
72SD3232
To [ACTV]: This command makes the other bank active. ( However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is
required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the operation is completed.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However,
Attempting to make the currently active bank active results in an illegal
an interval
command.
of
tRRD
is
required.)
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
www.DataSheeFtr4oUm.cRoEmAD with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM then enters precharge mode.
To [ACTV]: This command makes other banks active. (However, an interval of tRRD is required.) Attempting
to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active result in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP]: After an auto-refresh cycle (after tRC) the SDRAM automatically enters the IDLE state.
02.04.05 Rev 3
All data sheets are subject to change without notice 16
©2005 Maxwell Technologies
All rights reserved.










页数 41 页
下载[ 72SD3232.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
72SD32321 Gbit SDRAM 32-Meg X 32-Bit X 4-BanksMaxwell Technologies
Maxwell Technologies

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap