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PDF ( 数据手册 , 数据表 ) UDA1351H

零件编号 UDA1351H
描述 96 kHz IEC 958 audio DAC
制造商 NXP Semiconductors
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UDA1351H 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
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UDA1351H
96 kHz IEC 958 audio DAC
Preliminary specification
File under Integrated Circuits, IC01
2000 Feb 18







UDA1351H pdf, 数据表
Philips Semiconductors
96 kHz IEC 958 audio DAC
Preliminary specification
UDA1351H
www.DataSheet4U.com
handbook, full pagewidth
RESET 1
VDDD(C) 2
VSSD 3
VSSD(C) 4
L3DATA 5
L3CLOCK 6
DATAI 7
BCKI 8
WSI 9
L3MODE 10
n.c. 11
UDA1351H
33 BCKO
32 VDDA(PLL)
31 VSSA(PLL)
30 PREEM1
29 CLKOUT
28 n.c.
27 VDDA
26 VSSA
25 VSSA(DAC)
24 Vref
23 TC
MGL977
2000 Feb 18
Fig.2 Pin configuration.
8







UDA1351H equivalent, schematic
Philips Semiconductors
96 kHz IEC 958 audio DAC
Preliminary specification
UDA1351H
8.7 L3 interface
8.7.1 GENERAL
The UDA1351H has an L3 microcontroller interface and all
the digital sound processing features and various system
settings can be controlled by a microcontroller.
The controllable settings are:
www.DataSheet4RUe.csotomring L3 defaults
Power-on
Selection of input channel, clock source, DAC input and
external input format
Selection of filter mode and settings of treble and bass
boost
Volume settings
Selection of soft mute via cosine roll-off (only effective in
L3 control mode) and bypass of auto mute
Selection of de-emphasis.
The readable settings are:
Mute status of interpolator
PLL locked
SPDIF input signal locked
Audio Sample Frequency (ASF)
Valid PCM data detected
Pre-emphasis of the IEC 958 input signal
ACcuracy of the Clock (ACC).
The exchange of data and control information between the
microcontroller and the UDA1351H is LSB first and is
accomplished through a serial hardware L3 interface
comprising the following pins:
L3DATA: data line
L3MODE: mode line
L3CLK: clock line.
The exchange of bytes via the L3 interface is LSB first.
The L3 format has 2 modes of operation:
Address mode
Data transfer mode.
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6).
The data transfer mode is characterized by L3MODE
being HIGH and is used to transfer one or more bytes
representing a register address, instruction or data.
Basically 2 types of data transfers can be defined:
Write action: data transfer to the device
Read action: data transfer from the device.
Remark: when the device is powered up, at least one
L3CLOCK pulse must be given to the L3 interface to
wake-up the interface before starting sending to the device
(see Fig.6). This is only needed once after the device is
powered up.
8.7.2 DEVICE ADDRESSING
The device address consists of 1 byte with:
Bits 0 and 1 (called DOM bits) representing the type of
data transfer (see Table 5)
Bits 2 to 7 (address bits) representing a 6-bit device
address.
Table 5 Selection of data transfer
DOM
BIT 0
0
1
0
1
BIT 1
0
0
1
1
TRANSFER
not used
not used
write data or prepare read
read data
8.7.3 REGISTER ADDRESSING
After sending the device address, including Data
Operating Mode (DOM) bits indicating whether the
information is to be read or written, 1 data byte is sent
using bit 0 to indicate whether the information will be read
or written and bits 1 to 7 for the destination register
address.
Basically there are 3 methods for register addressing:
1. Addressing for write data: bit 0 is logic 0 indicating a
write action to the destination register, followed by
bits 1 to 7 indicating the register address (see Fig.6)
2. Addressing for prepare read: bit 0 is logic 1 indicating
that data will be read from the register (see Fig.7)
3. Addressing for data read action: in this case the device
returns a register address prior to sending data from
that register. When bit 0 is logic 0, the register address
is valid; in case bit 0 is logic 1 the register address is
invalid.
2000 Feb 18
16










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