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PDF ( 数据手册 , 数据表 ) JS29F16G08FANB1

零件编号 JS29F16G08FANB1
描述 (JS29FxxG08xANB1) SD74 NAND Flash Memory
制造商 Intel
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JS29F16G08FANB1 数据手册, 描述, 功能
Intel® SD74 NAND Flash Memory
w w w . D a t aJSS2h9Fe 0e4Gt 408UA.AcNBo 1m, JS29F08G08CANB1, JS29F16G08FANB1
Product Features
Datasheet
Single-level cell (SLC) Technology
Organization:
— Page size:
x8: 2,112 bytes (2,048 + 64 bytes)
— Block size: 64 pages (128K + 4K bytes)
— Plane size: 2,048 blocks
— Device size: 4Gb: 4,096 blocks; 8Gb: 8,192
blocks; 16Gb: 16,384 blocks
Read performance:
— Random read: 25µs (MAX)
— Sequential read: 25ns (MIN)
Write performance:
— Page program: 220µs (TYP)
— Block erase: 1.5ms (TYP)
Data Retention:
— 10 years
Endurance:
— 100,000 PROGRAM/ERASE cycles
First block (block address 00h):
— Guaranteed to be valid up to 1,000
PROGRAM/ERASE cycles
Vcc:
— 2.7V – 3.6V
Operating Temperature:
— –25 oC to 85 oC
Command set:
— Industry-standard basic NAND Flash
command set
Advanced Command Set:
— PROGRAM PAGE CACHE MODE
— PAGE READ CACHE MODE
— One-time programmable (OTP) commands
— Two-plane commands
— Interleaved die operation
— READ UNIQUE ID (contact factory)
— READ ID2 (contact factory)
— IwnittehrinnatlhDeaptlaanMeofvreo:mOwpehricahtiodnastasuisppreoartded
Operation status byte:
— Provides software method for detecting:
— Operation completion
— Pass/fail condition
— Write-protect status
Ready/busy# (R/B#) signal:
— PPrRoOvGidReAsMa ohrarEdRwAaSrEe cmyceltehocdomfoprledteiotencting
WP# signal:
— Write protect entire device
RESET:
— Required after power-up
Package Types:
— 48-pin TSOP Type 1
— 48-pin TSOP OCPL Type 1
Configuration:
# of Die # of CE# # of R/B# I/O
1 1 1 Common
2 2 2 Common
4 2 2 Common
Order Number: 312774-007US
8-Sep-2006







JS29F16G08FANB1 pdf, 数据表
Revision History
Intel® SD74 NAND Flash Memory
Date
8-Sep-06
www.DataSheet4U.com
22-Aug-06
1-Aug-06
29-Jun-06
15-Jun-06
02-Jun-06
08-Mar-06
Revision Description
• Added configuration table to title page.
007 • UInpfdoarmteadtitohne” oorndepraingge i7n4fo. rmation and part number decoder in Section 10.0, “Ordering
• Cdohcaunmgeedntthteo 8reGflbecptatrhtencuhmabnegrefrtoom2 JCSE2s9. F08G08BANB1 to JS29F08G08CANB1 throughout the
• Updated document to reflect 2 CE#s for the dual-die package device.
Section 7.2.4, “READ ID 90h” on page 32: Revised description.
• Package diagrams have been updated.
Figure 1, “Intel® SD74 NAND Flash Memory Functional Block Diagram” on page 10: Added “(2
planes)” to the NAND Flash Array.
Table 16, “Two-Plane Command Set” on page 30: Deleted “MULTIPLE-DIE READ STATUS” from
command 06h and updated note 3.
Section 7.7.2, “TWO-PLANE PAGE READ 00h-00h-30h” on page 44: Updated the fourth
paragraph.
Section 7.7.10, “TWO-PLANE/MULTIPLE-DIE READ STATUS 78h” on page 52: Updated first
006
paragraph and added a new paragraph at the end of the section.
Section 7.8, “Interleaved Die Operations” on page 53: Updated final paragraph.
Slaescttpioanra7g.r9a.p1h, .“RESET FFh” on page 59: Added “to all CE#s” and “and OTP operations” to the
Section 6.1, “Vcc Power Cycling” on page 24: Changed 1ms to 10µs in first paragraph; added
“to all CE#s” in last paragraph.
Figure 15, “AC Waveforms During Power Transitions” on page 25: Updated WE# signal.
Table 14, “PROGRAM/ERASE Characteristics” on page 28: Added note 4.
Figure 38, “TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle” on page 53: Added figure
showing all timing parameters.
Section 4.0, “Package Information” on page 16: Inserted recently updated versions of package
diagrams.
005
Updated the Operating Temperature range.
Updated with new product naming convention, and document title change.
004 Corrected typos in Section 6.0, “Electrical Characteristics”.
The maximum number of programming operations before an erase is required has been reduced
003 ftrhoemEl8ecttori4ca. lTChhisacrahcatnegriestiiscsrecfhleacptteedr iannTdabSleec1ti4o,n“7P.R3O.1G,R“APMRO/EGRRAASME PCAhGaEra8ct0ehr–is1t0ichs”” oonn ppaaggee 2386.in
• Adjusted Product Features section on page 1, including Write Performance Page Program
values from 150µs to 220µs
002 • Athdejupsrtoedduecltefcetaritcuarlesspseecciftiicoantioonnsp.aSgeee1S.ection 6.0, “Electrical Characteristics” on page 24 and
• Changes to Section 7.0, “Command Definitions” on page 29.
001 Initial Release.
DInatteal®shSeeDt74 NAND Flash Memory
8
8-Sep-2006
Order Number: 312774-007US







JS29F16G08FANB1 equivalent, schematic
Intel® SD74 NAND Flash Memory
4.0 Package Information
Figure 6. 48-pin TSOP
20.00 ±0.25
18.40 ±0.08
1
www.DataSheet4U.com
12.00 ±0.08
0.25
for reference only
0.50 TYP
for reference
48 only
Mold compound:
Epoxy novolac
Plated lead finish:
100% Sn
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
0.27 MAX
0.17 MIN
24 25
0.15
+0.03
-0.02
See detail A
1.20 MAX
N1.ote: All dimensions are in millimeters.
0.10
0.10
+0.10
-0.05
0.25
Gage
plane
0.50 ±0.1
0.80
Detail A
DInatteal®shSeeDt74 NAND Flash Memory
16
8-Sep-2006
Order Number: 312774-007US










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