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PDF ( 数据手册 , 数据表 ) S80C196NU

零件编号 S80C196NU
描述 COMMERCIAL CHMOS MICROCONTROLLER
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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S80C196NU 数据手册, 描述, 功能
PRELIMINARY
8XC196NU COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
s 50 MHz Operation
s 1 Mbyte of Linear Address Space
s Optional 48 Kbytes of ROM
s 1 Kbyte of Register RAM
s Register-register Architecture
s Footprint and Functionally Compatible
Upgrade for the 8XC196NP
s 32 I/O Port Pins
s 16 Prioritized Interrupt Sources
s 4 External Interrupt Pins and NMI Pin
s 2 Flexible 16-bit Timer/Counters with
www.DataSheet4U.cQomuadrature Counting Capability
s 3 Pulse-width Modulator (PWM)
Outputs with High Drive Capability
s Full-duplex Serial Port with Dedicated
Baud-rate Generator
s Peripheral Transaction Server
40 MHz standard; 50 MHz is Speed Premium
s Chip-select Unit
— 6 Chip-select Pins
— Dynamic Demultiplexed/Multiplexed
Address/Data Bus for Each
Chip Select
— Programmable Wait States
(0–3) for Each Chip Select
— Programmable Bus Width
(8- or 16-bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
s Event Processor Array (EPA) with
4 High-speed Capture/Compare
Channels
s Multiply and Accumulate Executes in
640 ns Using the 32-bit Hardware
Accumulator
s 960 ns 32/16 Unsigned Division
s 100-pin SQFP or 100-pin QFP Package
s Complete System Development
Support
s High-speed CHMOS Technology
The 8XC196NU is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation.
COPYRIGHT © INTEL CORPORATION, 1997
February 1997
Order Number: 272644-004







S80C196NU pdf, 数据表
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 80C196NU 100-pin SQFP Pin Assignment
Pin Name Pin Name Pin Name Pin Name
1 RESET#
26 EXTINT3/P3.7
51 CLKOUT/P2.7
76 WR#/WRL#
2 NMI
3 NC
4 A0
5 A1
6 VCC
7 VSS
8 A2
27 EPA0/P1.0
28 VCC
29 EPA1/P1.1
30 EPA2/P1.2
31 EPA3/P1.3
32 T1CLK/P1.4
33 T1DIR/P1.5
52 VCC
53 VSS
54 XTAL2
55 XTAL1
56 VSS
57 NC
58 A15
77 EPORT.3/A19
78 EPORT.2/A18
79 VSS
80 VCC
81 EPORT.1/A17
82 EPORT.0/A16
83 AD15
9 A3
10 A4
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12 A6
34 VCC
35 T2CLK/P1.6
36 VSS
37 T2DIR/P1.7
59 A14
60 A13
61 A12
62 A11
84 AD14
85 AD13
86 AD12
87 AD11
13 A7
38 PWM0/P4.0
63 A10
88 AD10
14 VCC
15 VSS
16 NC
17 PLLEN1
18 CS0#/P3.0
19 CS1#/P3.1
39 PWM1/P4.1
40 PWM2/P4.2
41 P4.3
42 VCC
43 VSS
44 TXD/P2.0
64 A9
65 A8
66 VSS
67 VCC
68 PLLEN2
69 ONCE
89 AD9
90 VSS
91 AD8
92 VCC
93 AD7
94 AD6
20 CS2#/P3.2
45 RXD/P2.1
70 RPD
95 AD5
21 CS3#/P3.3
46 EXTINT0/P2.2
71 READY
96 AD4
22 VSS
23 CS4#/P3.4
47 BREQ#/P2.3
48 EXTINT1/P2.4
72 INST
73 ALE
97 AD3
98 AD2
24 CS5#/P3.5
49 HOLD#/P2.5
74 BHE#/WRH#
99 AD1
25 EXTINT2/P3.6
50 HLDA#/P2.6
75 RD#
100 AD0
NOTE: To be compatible with future products, tie the NC (no connection) pins as follows: Pin 57 = VSS,
Pin 16 = VCC, and Pin 3 = NC.
4 PRELIMINARY







S80C196NU equivalent, schematic
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0 SIGNALS
Name
A15:0
A19:16
www.DataSheet4U.com
AD15:0
ALE
Type
I/O
I/O
I/O
O
Table 8. Signal Descriptions
Description
System Address Bus
These address lines provide address bits 0–15 during the entire external mem-
ory cycle during both multiplexed and demultiplexed bus modes.
Address Lines 16–19
These address lines provide address bits 16–19 during the entire external
memory cycle, supporting extended addressing of the 1 Mbyte address space.
NOTE:
Internally, there are 24 address bits; however, only 20 external
address pins (A19:0) are implemented. The internal address space is
16 Mbytes (000000–FFFFFFH) and the external address space is
1 Mbyte (00000–FFFFFH). The device resets to FF2080H in internal
memory or F2080H in external memory.
A19:16 are multiplexed with EPORT.3:0.
Address/Data Lines
The functions of these pins depend on the bus size and mode. When a bus
access is not occurring, these pins revert to their I/O port function.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drive or
receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive
address bits 0–7 during the first half of the bus cycle and drive or receive data
during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data
that is currently on the high byte of the internal bus.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus (A19:16 and AD15:0 for
a multiplexed bus; A19:0 for a demultiplexed bus). ALE differs from ADV# in that
it does not remain active during the entire bus cycle.
An external latch can use this signal to demultiplex the address bits 0–15 from
the address/data bus in multiplexed mode.
12 PRELIMINARY










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