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PDF ( 数据手册 , 数据表 ) E5108ASE

零件编号 E5108ASE
描述 EDE5108ASE
制造商 Elpida Memory
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E5108ASE 数据手册, 描述, 功能
PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AGSE (128M words × 4 bits)
EDE5108AGSE (64M words × 8 bits)
Description
The EDE5104AGSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108AGSE is a 512M bits DDR2 SDRAM
www.DataSheet4Uo.crogmanized as 16,777,216 words × 8 bits × 4 banks.
They are packaged in 60-ball FBGA (µBGA) package.
Features
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
SSTL_18 compatible I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0715E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005







E5108ASE pdf, 数据表
EDE5104AGSE, EDE5108AGSE
max.
Parameter
Symbol Grade × 4 × 8 Unit Test condition
Auto-refresh current IDD5
-6C
-6E
-5C
-4A
TBD
270
250
230
TBD
270
250
230
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current IDD6
Self Refresh Mode;
CK and /CK at 0V;
6 6 mA CKE 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
www.DataSheet4UO.cpoemrating current
(Bank interleaving)
IDD7
-6C
-6E
-5C
-4A
TBD
300
300
280
TBD
320
320
300
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD),
AL = tRCD (IDD) 1 × tCK (IDD);
mA
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN VIL (AC) (max.)
H is defined as VIN VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
DDR2-667
DDR2-533
Parameter
CL(IDD)
4-4-4
4
5-5-5
5
4-4-4
4
tRCD(IDD)
12 15 15
tRC(IDD)
57 60 60
tRRD(IDD)
7.5 7.5 7.5
tCK(IDD)
3 3 3.75
tRAS(min.)(IDD)
45
45 45
tRAS(max.)(IDD)
70000
70000
70000
tRP(IDD)
12 15 15
tRFC(IDD)
105 105 105
DDR2-400
3-3-3
3
15
55
7.5
5
40
70000
15
105
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet E0715E20 (Ver. 2.0)
8







E5108ASE equivalent, schematic
EDE5104AGSE, EDE5108AGSE
Pin Function
CK, /CK (input pins)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with
multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
www.DataSheet4UA.c0omto A13 (input pins)
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the respective bank. The address inputs also provide
the op-code during mode register set commands.
[Address Pins Table]
Part number
EDE5104AGSE
EDE5108AGSE
Address (A0 to A13)
Row address
AX0 to AX13
AX0 to AX13
Column address
AY0 to AY9, AY11
AY0 to AY9
Note
A10 (AP) (input pin)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1.
BA0, BA1 (input pins)
BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also
determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
[Bank Select Signal Table]
Bank 0
Bank 1
Bank 2
Bank 3
Remark: H: VIH. L: VIL.
BA0
L
H
L
H
BA1
L
L
H
H
CKE (input pin)
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.
Taking CKE low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down
(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is
asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-
refresh.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
16










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