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PDF ( 数据手册 , 数据表 ) ZL10060

零件编号 ZL10060
描述 MOPLL
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL10060 数据手册, 描述, 功能
ZL10060
MOPLL with IF AGC Amplifier
Data Sheet
Features
• Highly integrated mixer/oscillator PLL and IF AGC
amplifier for multi band analog/digital terrestrial
tuners and/or cable tuners
• Low phase noise PLL frequency synthesizer
• AGC output level detect with digital controlled
TOP threshold
• >50 dB Desired/Undesired ratio without pre
www.DataSheet4Uf.iclotemring
• Separate analog and digital IF outputs
• >41 dB IF AGC Control range
• Power down modes to support power reduction
initiatives
• Four independent GPO
• 48 pin QFN Package
Applications
• DVB-T receiver systems
• ISDB-T receiver systems
• DVB-C cable receiver systems
• Terrestrial analog receivers
November 2005
Ordering Information
ZL10060LDG1 48 Pin QFN* Trays
ZL10060LDF1 48 Pin QFN* Tape and Reel
*Pb Free Matte Tin
-20°C to +85°C
Description
The ZL10060 is a 3 band MOPLL with IF AGC
amplifier. It down-converts the RF channel to a
standard IF followed by filtering and IF AGC
amplification for the digital channel. Each band
consists of a low noise preamplifier/mixer and local
oscillator with an external varactor tuned tank circuit.
An IF level detector is included for control of the RF
AGC. The Take Over Point and time constant are both
programmable.
The ZL10060 has high signal level handling
performance providing excellent performance in the
presence of high level unwanted signals.
All chip control is via I2C bus.
If higher performance is required, an alternative part,
ZL10063 is available with image reject down
conversion.
RF
Input
ZL10060
GPO
RF AGC
Tuning
VCO Tank
Circuits
Band
Pass
Filter
Analog Digital
IF SAW IF SAW
Analog
Analog IF Demod
PLL
AGC
Det
I2C
Control
Digital IF
Digital
Demod
IF AGC
I2C
Loop
Filter
Figure 1 - Basic Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.







ZL10060 pdf, 数据表
ZL10060
Data Sheet
An AGC IF amplifier is included which provides an output signal to a digital demodulator.
The device is controlled through an I2C compatible interface.
1.1 RF Converter
The ZL10060 contains three input stages to cover the VHF1, VHF3 and UHF frequency bands. The inputs would
normally be driven by front end amplifiers and tracking filters. All three inputs are differential, however, the VHF1
and VHF3 inputs would normally be single ended. These inputs therefore can share a common input reference pin.
The UHF input should be driven with a differential signal. The inputs are all high impedance. The differential
converter IF output is then passed through an external interstage filter. This can be tuned for 36 MHz for DVB-T
applications but can also be used at 44 MHz and 57 MHz to be compatible with other TV standards. The
recommended filter circuit is shown in Figure 9. The design of this filter provides an impedance transformation as
well as rejection of adjacent channels. A 0.5 dB Chebychev filter with 10 MHz bandwidth is recommended. This
www.DataSheegt4ivUe.csoamflat response across the pass band and takes into account normal component tolerances.
1.2 SAW Driver Amplifier
The output of the interstage filter then passes to the SAW filter drive amplifier. This provides further amplification
and interfaces to the SAW filter. Two SAW filter drive outputs are provided for hybrid analog and digital applications.
Both output stages are identical however the digital output (SD, SDB) should always be used for digital applications
as the pin out of the device has been optimized to give the best isolation performance in this configuration. Output
selection is programmable however it should be noted that the unselected output is not powered off but operates at
a lower power level which means that a signal will still be present on the output.
The differential outputs will drive a balanced SAW filter with a tuning inductor to resonate with the SAW filter input
capacitance. The SAW filter can also be driven without the tuning inductor but with the addition of 350 ohm resistors
to ground on the SAW driver outputs to increase the output drive capability. This will increase total current
consumption by 14 mA.
1.3 AGC Detector and ADC
The ZL10060 contains a broadband AGC detector circuit which provides an output to provide gain control for the
RF frontend gain stages. The detector input signal is derived from the signal level in the SAW driver amplifier. The
composite signal at this point is the wanted signal plus adjacent channels (N +/- 1, N +/- 2, N +/- 3). The AGC
detector threshold point at which the agc output becomes active can be programmed to one of eight levels via the
I2C interface. When the composite level reaches the agc threshold, the agc output pin will be active. The AGC
attack current is fixed, however, the decay current can be programmed to two levels. The agc output can only drive
a high impedance e.g., a dual gate FET. If RF gain control uses a PiN diode then a simple buffer circuit will be
required.
An AGC flag output is also available through the I2C interface. This indicates when the AGC output is active i.e.,
less than 4 volts.
The agc output level can also be monitored by an on chip 3 bit ADC. Although the ADC is 3 bits, only 5 levels are
available. Alternatively the ADC can be programmed to measure the voltage on an external pin (ADC Pin 4).
1.4 IF AGC Amplifier
The AGC amplifier amplifies the output of the SAW filter for the digital channel and provides a differential output to
the demodulator. The analog gain control signal is normally derived from the demodulator. At least 41 dB of gain
control is provided.
The AGC amplifier can be powered down independently of the rest of the device if not required. This mode could be
used in analog applications to reduce overall power consumption.
8
Zarlink Semiconductor Inc.







ZL10060 equivalent, schematic
ZL10060
Data Sheet
2.6 Control Register - Byte 6
Bit Field
Name
Default
Description
7 LO1 0 VCO Bias Trim
6 LO0 0 Not used
5
ATC
0 AGC Decay current select
4 IFE 0 IF AGC Amplifier enable (1 = On)
3 X 0 Not used
2:0
AT[2:0]
0 AGC Threshold Select
www.DataSheet4U.com
Table 14 - Byte 6 Control
The VCO bias trim adjusts the VCO bias to give optimum close-in phase noise. In general this should be set to 1 for
the lower third of the VCO frequency range.
The AGC attack current is fixed at 100 µA however the agc decay current can be programmed to one of two values
as shown below. If the PLL is unlocked (FL = 0), then the ATC control is over-ridden and the AGC decay current is
set to 10µA. When the PLL locks (FL = 1) the decay current reverts to the programmed ATC value.
ATC AGC Decay Current (µA)
0 10.0
1 0.3
Table 15 - AGC Decay Current Setting
16
Zarlink Semiconductor Inc.










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