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PDF ( 数据手册 , 数据表 ) N80C196KQ

零件编号 N80C196KQ
描述 (N80C196xx) COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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N80C196KQ 数据手册, 描述, 功能
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87C196KR KQ 87C196JV JT 87C196JR JQ
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y b40 C to a125 C Ambient
Y High Performance CHMOS 16-Bit CPU
Y Up to 48 Kbytes of On-Chip EPROM
Y Up to 1 5 Kbytes of On-Chip Register
RAM
Y Up to 512 Bytes of Additional RAM
(Code RAM)
Y Register-Register Architecture
Y Up to 8 Channel 10-Bit A D with
Sample Hold
Y Up to 37 Prioritized Interrupt Sources
Y Up to Seven 8-Bit (56) I O Ports
Y Full Duplex Serial I O Port
Y Dedicated Baud Rate Generator
Y Interprocessor Communication Slave
Port
Y High Speed Peripheral Transaction
Server (PTS)
Y Two 16-Bit Software Timers
Y 10 High Speed Capture Compare (EPA)
Y Full Duplex Synchronous Serial I O
Port (SSIO)
Y Two Flexible 16-Bit Timer Counters
Y Quadrature Counting Inputs
Y Flexible 8- 16-Bit External Bus
Y Programmable Bus (HLD HLDA)
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y 68-Pin and 52-Pin PLCC Packages
Device Pins Package EPROM Reg RAM Code RAM I O EPA SIO SSIO A D
87C196KR 68-pin PLCC
16K
488
256 56 10 Y Y 8
87C196KQ 68-pin PLCC
12K
360
128 56 10 Y Y 8
87C196JV 52-pin PLCC 48K 1 5K
512
41 6
Y
Y
6
87C196JT 52-pin PLCC 32K 1 0K
512
41 6
Y
Y
6
87C196JR 52-pin PLCC
16K
488
256
41 6
Y
Y
6
87C196JQ 52-pin PLCC
12K
360
128
41 6
Y
Y
6
The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller prod-
ucts implemented on Intel’s advanced 1 micron process technology These products are based on the
80C196KB device with improvements for automotive applications The instruction set is a true super set of
80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory
scalars of the 87C196KR JR
The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family
These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and
electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512
bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes
of Code RAM
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 270827-006







N80C196KQ pdf, 数据表
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87C196KR KQ 87C196JV JT 87C196JR JQ
DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)
Symbol
Parameter
Min Typ
Max Units
Test Conditions
VOH
ILI
Output High Voltage
(Outputs Configured
as Push Pull)
Input Leakage Current
(Std Inputs)
VCC b 0 3
VCC b 0 7
VCC b 1 5
V IOH e b200 mA (Notes 3 5)
V IOH e b3 2 mA
V IOH e b7 0 mA
g8 mA VSS s VIN s VCC
JT JV g10
(Note 2)
ILI1 Input Leakage Current
(Port 0 A D Inputs)
g1 mA VSS s VIN s VREF
JT JV g2
IIH Input High Current
(NMI Pin)
a175
mA VSS s VIN s VCC
VOH2
Output High Voltage
in RESET
VCC b 1V
V IOH e b15 mA (Notes 1 8)
IOH2
(KR KQ)
Output High Current
in RESET
IOH2
(JV JT
Output High
Current in
JR-D JQ-D) RESET
RRST
VOL3
Reset Pullup Resistor
Output Low Voltage
in RESET
(RESET Pin only)
CS
RWPU
Pin Capacitance
(Any Pin to VSS)
Weak Pullup Resistance
(Approx)
b6
b15
b20
b30
b75
b90
6K
150K
b35
b60
b70
b120
b240
b280
65K
03
05
08
10
mA VOH2 e VCC b 1 0V
mA VOH2 e VCC b 2 5V
mA VOH2 e VCC b 4 0V
mA VOH2 e VCC b 1 0V
mA VOH2 e VCC b 2 5V
mA VOH2 e VCC b 4 0V
X
V IOL3 e 4 mA (Note 9)
V IOL3 e 6 mA
V IOL3 e 10 mA
pF FTEST e 1 0 MHz
X (Note 6)
NOTES
1 All BD (bidirectional) pins except P5 1 INST and P2 7 CLKOUT which are excluded due to their not being weakly pulled
high in reset BD pins include Port1 Port2 Port3 Port4 Port5 and Port6
2 Standard Input pins include XTAL1 EA RESET and Ports 1 2 3 4 5 6 when configured as inputs
3 All Bidirectional I O pins when configured as Outputs (Push Pull)
4 Device is Static and should operate below 1 Hz but only tested down to 4 MHz
5 Maximum IOL IOH currents per pin will be characterized and published at a later date Target values are g10 mA
6 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and
VREF e VCC e 5 0V
7 VIH max for Port0 is VREF a 0 5V
8 Refer to ‘‘VOH2 IOH2 Specification’’ errata 1 in errata section of this datasheet
9 This specification is not tested in production and is based upon theoretical estimates and or product characterization
8







N80C196KQ equivalent, schematic
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87C196KR KQ 87C196JV JT 87C196JR JQ
A TO D CONVERTER SPECIFICATIONS
The speed of the A D converter in the 10-bit or 8-bit
modes can be adjusted by setting the AD TIME
special function register to the appropriate value
The AD TIME register only programs the speed at
which the conversions are performed not the speed
at which it can convert correctly
VREF must not exceed VCC by more than 0 5V since
it supplies both the resistor ladder and the digital
portion of the converter and input port pins
For testing purposes after a conversion is started
the device is placed in the IDLE mode until the con-
version is complete Testing is performed at VREF e
5 12V and 16 MHz operating frequency
The converter is ratiometric so absolute accuracy is
dependent on the accuracy and stability of VREF
A D OPERATING CONDITIONS(1)
There is an AD TEST register that allows for con-
version on ANGND and VREF as well as zero offset
adjustment The absolute error listed is without do-
ing any adjustments
Symbol
Description
Min
Max
Units
TA
VCC
VREF
TSAM
TCONV
FOSC
Automotive Ambient Temperature
Digital Supply Voltage
Analog Supply Voltage
Sample Time
Conversion Time
Oscillator Frequency
b40
4 50
4 50
20
16 5
4
a125
5 50
5 50(2 3)
19 5
16
C
V
V
ms(4)
ms(4)
MHz
NOTES
1 ANGND and VSS should nominally be at the same potential
2 VREF must not exceed VCC by more than a0 5V
3 Testing is performed at VREF e 5 12V
4 The value of AD TIME must be selected to meet these specifications
Parameter
Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
Temperature Coefficients
Offset
Fullscale
Differential Non-Linearity
Off Isolation
Feedthrough
VCC Power Supply Rejection
Input Resistance
DC Input Leakage
Typical (1)
g2
g2
g0 25
0 009
0 009
0 009
b60
b60
Min
1024
10
0
l b0 5
0
0
b60
750
0
Max
1024
10
b3
a3
g3
a0 5
g1
1 2K
g1
JT JV e g2
Units
Level
Bits
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs(1)
LSB C(1)
LSB C(1)
LSB C(1)
dB(1 2 3)
dB(1 2)
dB(1 2)
X(1)
mA
NOTES
These values are expected for most parts at 25 C but are not tested or guaranteed
An ‘‘LSB’’ as used here has a value of approximately 5 mV (See Automotive Handbook for A D glossary of terms)
1 These values are not tested in production and are based on theoretical estimates and or laboratory test
2 DC to 100 KHz
3 Multiplexer Break-Before-Make Guaranteed
16










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