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PDF ( 数据手册 , 数据表 ) ADC-0803

零件编号 ADC-0803
描述 (ADC0802 - ADC0804) 8-Bit/ Microprocessor- Compatible/ A/D Converters
制造商 Harris
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ADC-0803 数据手册, 描述, 功能
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Semiconductor
August 1997
ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
Compatible, A/D Converters
Features
Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
The ADC0802 family are CMOS 8-Bit, successive-approxi-
mation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Ordering Information
PART NUMBER
ADC0802LCN
ADC0802LCD
ADC0802LD
ADC0803LCN
ADC0803LCD
ADC0803LCWM
ADC0803LD
ADC0804LCN
ADC0804LCD
ADC0804LCWM
ERROR
±1/2 LSB
±3/4 LSB
±1 LSB
±1/2 LSB
±3/4 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 = 2.500VDC (No Adjustments)
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
PKG. NO
E20.3
F20.3
F20.3
E20.3
F20.3
M20.3
F20.3
E20.3
F20.3
M20.3
Pinout
Typical Application Schematic
ADC0802, ADC0803, ADC0804
(PDIP, CERDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
ANY
µPROCESSOR
1 CS
2 RD
V+ 20
CLK R 19
+5V 150pF
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
VREF/2
DGND
6
7
8
9
10
DIFF
INPUTS
VREF/2
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
6-5
File Number 3094.1







ADC-0803 pdf, 数据表
www.DataSheet4U.com
ADC0802, ADC0803, ADC0804
D+1
D
D-1
56
34
12
+1 LSB
+1/2 LSB
0
-1/2 LSB
135
* QUANTIZATION ERROR
2 46
A-1 A A+1
-1 LSB
A-1 A A+1
ANALOG INPUT (VIN)
ANALOG INPUT (VIN)
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11A. ACCURACY = ±0 LSB; PERFECT A/D
+1 LSB
D+1
D
D-1
5
6
3
4
1
2
A-1 A A+1
0
-1 LSB
1
3 6 * QUANTIZATION
ERROR
4
2
A-1 A A+1
ANALOG INPUT (VIN)
ANALOG INPUT (VIN)
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11B. ACCURACY = ±1/2 LSB
FIGURE 11. CLARIFYING THE ERROR SPECS OF AN A/D CONVERTER
Understanding A/D Error Specs
A perfect A/D transfer characteristic (staircase wave-form) is
shown in Figure 11A. The horizontal scale is analog input volt-
age and the particular points labeled are in steps of 1 LSB
(19.53mV with 2.5V tied to the VREF/2 pin). The digital output
codes which correspond to these inputs are shown as D-1, D,
and D+1. For the perfect A/D, not only will center-value (A - 1,
A, A + 1, . . .) analog inputs produce the correct output digital
codes, but also each riser (the transitions between adjacent
output codes) will be located ±1/2 LSB away from each center-
value. As shown, the risers are ideal and have no width. Correct
digital output codes will be provided for a range of analog input
voltages which extend ±1/2 LSB from the ideal center-values.
Each tread (the range of analog input voltage which provides
the same digital output code) is therefore 1 LSB wide.
The error curve of Figure 11B shows the worst case transfer
function for the ADC0802. Here the specification guarantees
that if we apply an analog input equal to the LSB analog volt-
age center-value, the A/D will produce the correct digital code.
Next to each transfer function is shown the corresponding error
plot. Notice that the error includes the quantization uncertainty of
the A/D. For example, the error at point 1 of Figure 11A is
+1/2 LSB because the digital code appeared 1/2 LSB in advance
of the center-value of the tread. The error plots always have a
constant negative slope and the abrupt upside steps are always
1 LSB in magnitude, unless the device has missing codes.
Detailed Description
The functional diagram of the ADC0802 series of A/D
converters operates on the successive approximation princi-
ple (see Application Notes AN016 and AN020 for a more
detailed description of this principle). Analog switches are
closed sequentially by successive-approximation logic until
the analog differential input voltage [VlN(+) - VlN(-)] matches
a voltage derived from a tapped resistor string across the
reference voltage. The most significant bit is tested first and
after 8 comparisons (64 clock cycles), an 8-bit binary code
(1111 1111 = full scale) is transferred to an output latch.
The normal operation proceeds as follows. On the high-to-low
transition of the WR input, the internal SAR latches and the
shift-register stages are reset, and the INTR output will be set
high. As long as the CS input and WR input remain low, the
A/D will remain in a reset state. Conversion will start from 1 to
8 clock periods after at least one of these inputs makes a low-
to-high transition. After the requisite number of clock pulses to
complete the conversion, the INTR pin will make a high-to-low
transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion. A RD
operation (with CS low) will clear the INTR line high again.
6-12







ADC-0803 equivalent, schematic
www.DataSheet4U.com
ADC0802, ADC0803, ADC0804
Die Characteristics
DIE DIMENSIONS:
(101 mils x 93 mils) x 525µm x 25µm
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
Metallization Mask Layout
PASSIVATION:
Type: Nitride over Silox
Nitride Thickness: 8kÅ
Silox Thickness: 7kÅ
ADC0802, ADC0803, ADC0804
AGND
VIN (-)
VIN (+)
INTR CLK IN
WR
VREF/2
DGND
DB7 (MSB)
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RD
CS
V+ OR VREF
V+ OR VREF
CLK R
6-20










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