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PDF ( 数据手册 , 数据表 ) 39SF512

零件编号 39SF512
描述 SST39SF512
制造商 SST
LOGO SST LOGO 


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39SF512 数据手册, 描述, 功能
www.DataSheet4U.com
512 Kbit (x8) Multi-Purpose Flash
SST39SF512
FEATURES:
SST39SF5125.0V 512Kb (x8) MPF memory
Data Sheet
• Organized as 64K x8
• Single 4.5-5.5V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 10 mA (typical)
– Standby Current: 10 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Byte-Program
– Sector-Erase Time: 7 ms (typical)
– Chip-Erase Time: 15 ms (typical)
– Byte-Program Time: 20 µs (typical)
– Chip Rewrite Time: 2 seconds (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF512 are CMOS Multi-Purpose Flash (MPF)
manufactured with SST’s proprietary, high performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST39SF512 devices write (Program or Erase) with a
4.5-5.5V power supply. The SST39SF512 device conforms
to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF512 devices provide a maximum Byte-Program
time of 30 µsec. These devices use Toggle Bit or Data#
Polling to indicate the completion of Program operation. To
protect against inadvertent write, they have on-chip hard-
ware and Software Data Protection schemes. Designed,
manufactured, and tested for a wide spectrum of applica-
tions, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF512 devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during erase and program than alternative flash
technologies. The total energy consumed is a function of
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
1
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF512 are offered in 32-lead PLCC, 32-lead TSOP,
and a 600 mil, 32-pin PDIP packages. See Figures 1, 2,
and 3 for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.







39SF512 pdf, 数据表
www.DataSheet4U.com
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V1
Limits
Symbol Parameter
Min Max Units Test Conditions
IDD Power Supply Current
Read2
Program and Erase
ISB1 Standby VDD Current
(TTL input)
Address input=VILT/VIHT, at f=1/TRC Min
VDD=VDD Max
30 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
50 mA CE#=WE#=VIL, OE#=VIH
3 µA CE#=VIH, VDD=VDD Max
ISB2 Standby VDD Current
(CMOS input)
50 µA CE#=VDD -0.3V, VDD=VDD Max
ILI Input Leakage Current
1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current
10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage
0.8 V VDD=VDD Min
VIH Input High Voltage
2.0
V VDD=VDD Max
VOL Output Low Voltage
0.4 V IOL=2.1 mA, VDD=VDD Min
VOH Output High Voltage
2.4
V IOH=-400 µA, VDD=VDD Min
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 5V for SF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
T5.6 1149
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1 Power-up to Read Operation
100 µs
TPU-WRITE1 Power-up to Program/Erase Operation
100 µs
T6.1 1149
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description
Test Condition
Maximum
CI/O1
CIN1
I/O Pin Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
12 pF
6 pF
T7.0 1149
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1,2
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA JEDEC Standard 78
T8.2 1149
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2003 Silicon Storage Technology, Inc.
8
S71149-05-000
11/03







39SF512 equivalent, schematic
www.DataSheet4U.com
Data Sheet
512 Kbit Multi-Purpose Flash
SST39SF512
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Byte
Address/Byte
Data
Wait for end of
Program (TBP'
Data# Polling
bit or Toggle bit
operation)
Program
Completed
1149 F13.1
FIGURE 15: BYTE-PROGRAM ALGORITHM
©2003 Silicon Storage Technology, Inc.
16
S71149-05-000
11/03










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