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PDF ( 数据手册 , 数据表 ) STA120

零件编号 STA120
描述 DIGITAL AUDIO INTERFACE RECEIVER
制造商 STMicroelectronics
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STA120 数据手册, 描述, 功能
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STA120
DIGITAL AUDIO INTERFACE RECEIVER
s MONOLITHIC CMOS RECEIVER
s 3.3V SUPPLY VOLTAGE
s LOW-JITTER, ON-CHIP CLOCK RECOVERY
256xFs OUTPUT CLOCK PROVIDED
s SUPPORTS: AES/EBU, IEC 958, S/PDIF, &
EIAJ CP-340/1201 PROFESSIONAL AND
CONSUMER FORMATS
s EXTENSIVE ERROR REPORTING REPEAT
LAST SAMPLE ON ERROR OPTION
DESCRIPTION
The STA120 is a monolithic CMOS device that re-
ceives and decodes audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201
interface standards.
The STA120 recovers the clock and synchroniza-
BLOCK DIAGRAM
SO28
ORDERING NUMBER: STA120D
tion signals and de-multiplexes the audio and dig-
ital data. Differential or single ended inputs can be
decoded.
The STA120 de-multiplexes the channel, user and
validity data directly to serial output pins with ded-
icated output pins for the most important channel
status bits.
VD+ DGND
78
VA+ FILT AGND MCK
22 20 21 19
RXP
RXN
9
RS422
10 Receiver
MUX
CLOCK & DATA
RECOVERY
DE MUX
MUX
M3 M2 M1 M0
17 18 24 23
AUDIO
SERIAL PORT
REGISTERS
26
SDATA
12
SCK
11
FSYNC
1
C
14
U
28
VREF
13
CS12/FCK
16 6 5 4 3 2 27
SEL C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2
25
ERF
15
CBL D97AU613A
December 2002
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STA120 pdf, 数据表
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STA120
This timing is illustrated in Figure 5.
The C output contains the channel status bits with CBL rising indicating the start of a new channel status
block. CBL is high for the first four bytes of channel status (32 frames or 64 samples) and low for the last
20 bytes of channel status (160 frames or 320 samples).
The U output contains the User Channel data. The V bit is OR'ed with the ERF flag and output on the
VERF pin. This indicates that the audio sample may be in error and can be used by interpolation filters to
interpolate through the error.
ERF being high indicates a serious error occurred on the transmission line. There are three errors that
cause ERF to go high: a parity error or biphase coding violation during that sample, or an out of lock PLL
receiver. Timing for the above pins is illustrated in Figure 5.
Multifunction Pins
There are seven multifunction pins which contain either error and received frequency information, or chan-
nel status information, selectable by SEL.
Figure 3. Audio Serial Port Formats
FORMAT 0:
M2
0
M1
0
M0
0
FSYNC(out)
SCK(out)
LEFT
RIGHT
SDATA(out)
FORMAT 1:
FSYNC(in)
001
SCK(in)
MSB
LSB
LEFT
MSB
LSB
RIGHT
MSB
SDATA(out)
FORMAT 2:
01
FSYNC(out)
0
SCK(out)
MSB
LEFT
LSB MSB
RIGHT
LSB MSB
SDATA(out)
FORMAT 3:
FSYNC(in)
011
SCK(in)
MSB
LSB
LEFT
MSB
LSB
RIGHT
MSB
SDATA(out)
FORMAT 4:
10
FSYNC(out)
0
SCK(out)
MSB
LSB
LEFT
MSB
LSB
RIGHT
MSB
SDATA(out)
FORMAT 5:
10
FSYNC(out)
1
SCK(out)
MSB
LSB
LEFT
MSB
LSB
RIGHT
MSB
SDATA(out) LSB
MSB
LSB
MSB
LSB
FORMAT 6:
11
FSYNC(out)
0
SCK(out)
16 Bits
LEFT
16 Bits
RIGHT
SDATA(out) LSB
MSB
LSB
MSB
LSB
FORMAT 7:
11
FSYNC(out)
1
SCK(out)
18 Bits
LEFT
18 Bits
RIGHT
SDATA(out) MSB LSB MSB
LSB MSB
D97AU610
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