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PDF ( 数据手册 , 数据表 ) K8F5715ETM

零件编号 K8F5715ETM
描述 256Mb M-die MLC NOR Specification
制造商 Samsung Electronics
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K8F5715ETM 数据手册, 描述, 功能
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K8F56(57)15ET(B)M
NOR FLASH MEMORY
256Mb M-die MLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 Revision 1.2
September, 2006







K8F5715ETM pdf, 数据表
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K8F56(57)15ET(B)M
NOR FLASH MEMORY
Table 3-1. K8F56(57)15ETM DEVICE BANK DIVISIONS (Top Boot Block)
Bank
0
Quantity of Blocks
4
15
1 16
2 16
3 16
4 16
5 16
6 16
7 16
8 16
9 16
10 16
11 16
12 16
13 16
14 16
15 16
Block Size
16 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Table 3-2. K8F56(57)15EBM DEVICE BANK DIVISIONS (Bottom Boot Block)
Bank
15
Quantity of Blocks
16
14 16
13 16
12 16
11 16
10 16
9 16
8 16
7 16
6 16
5 16
4 16
3 16
2 16
1 16
15
0
4
Block Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
16 Kwords
8 Revision 1.2
September, 2006







K8F5715ETM equivalent, schematic
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K8F56(57)15ET(B)M
NOR FLASH MEMORY
Accelerated Program
The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the
factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily
unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In
accelerated program mode, the system would use a two-cycle program command sequence for only a word program. By removing
VID returns the device to normal operation mode.
Note that Read While Accelerated Program and Program suspend mode are not guaranteed.
Program/Erase cycling must be limited below 100cycles for optimum performance.
Ambient temperature requirements : TA = 30°C±10°C
Single word accelerated program operation
The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-
cycle (PA - PD) is for program address and data)
Writer Buffer Programming
Write Buffer Programming allows the system write to a maximum of 32 words in one programming operation. This results in faster
effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-
ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the
block address in which programming will occur. The fourth cycle writes the block address and the number of word locations, minus
one, to be programmed. For example, if the system will program 19 unique address locations, then 12h should be written to the
device. This tells the device how many write buffer addresses will be loaded with data. The number of locations to program cannot
exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be pro-
grammed. The write-buffer-page is selected by address bits A23(max.) ~ A5 entered at fifth cycle. All subsequent address/
data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit
A23(max.) ~ A5 as those entered at fifth cycle. Write buffer locations may be loaded in any order.
Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com
mand at the block address. Any other command address/data combination aborts the Write Buffer Programming operation. The
device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer.
DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer
programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of
the Write Buffer Programming operation, the device is ready to execute the next command. Note also that an address loaction can-
not be loaded more than once into the write-buffer-page.
The Write Buffer Programming Sequence can be aborted in the following ways:
Loading a value that is greater than the buffer size(32-words) during then number of word locations to Program step.
(In case, WC > 1FH @Table5 )
The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table5)
Writing a Program address to have a different write-buffer-page with selected write-buffer-page
( Address bits A23(max) ~ A5 are different)
Writing non-exact "Program Buffer to Flash" command
The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-
to-Buffer-Abort Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of
Write-to-Buffer-Abort Reset command sequence(XXXh-F0h) is required when using Write-Buffer-Programming features in Unlock
Bypass mode. And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Pro-
gramming features in Unlock Bypass mode. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the
device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read
will show that the data is still “0.” Only erase operations can convert a “0” to a “1."
Accelerated Write Buffer Programming
The device provides accelerated Write Buffer Program operations through the Vpp input. Using this mode, faster manufacturing
throughput at the factory is possible. When VID is asserted on the Vpp input, the device temporarily unprotects any protected blocks,
and uses the higher voltage on the input to reduce the time required for program operations. In accelerated Write Buffer Program
mode, the system must enter "Write to Buffer" and "Program Buffer to Flash" command sequence to be same as them of normal
Write Buffer Programming and only can reduce the program time. Note that the third cycle of "Write to Buffer Abort Reset" command
sequence(XXXh-F0h) is required to reset the device for the next operation in an Accelerated mode.
Note that Read While Accelerated Write Buffer Program and Program suspend mode are not guaranteed.
Program/Erase cycling must be limited below 100cycles for optimum performance.
16 Revision 1.2
September, 2006










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