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PDF ( 数据手册 , 数据表 ) D72103A

零件编号 D72103A
描述 UPD72103A
制造商 NEC
LOGO NEC LOGO 


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D72103A 数据手册, 描述, 功能
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µPD72103A
HDLC CONTROLLER
© 1997
µPD72103A
Document No. S10766EJ9V0UM00 (9th edition)
Date Published March 1997 N CP(N)
Printed in Japan







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LIST OF FIGURE
Figure No.
Title Page
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
Control Register ....................................................................................................................................... 14
Internal Status Register ........................................................................................................................... 15
Basic Clocks in One Bus Cycle during Block Transfer .......................................................................... 16
Example: Two Programmable Waits ...................................................................................................... 17
Memory Write Timing ............................................................................................................................... 18
Memory Read Timing ............................................................................................................................... 19
Byte Mode (B/W = 0) ............................................................................................................................... 20
Word Mode (B/W = 1) .............................................................................................................................. 21
Command/Status Handling between µPD72103A and Host Processor ................................................ 22
Flow Chart for Writing “Memory Area Setting LCW” Command to Internal FIFO ................................. 24
Status Report (when Status Area is LSW0 to LSW2) ............................................................................ 26
Command Table ....................................................................................................................................... 28
Command Fetch Operation ..................................................................................................................... 30
Status Table .............................................................................................................................................. 32
Status Information Operations ................................................................................................................ 34
Receive Buffer Address Table ................................................................................................................. 36
Initial Status (Line Closed) ...................................................................................................................... 38
After Line Open Command Is Issued ...................................................................................................... 39
RBAFIFO Full Status ............................................................................................................................... 40
Reception of First Frame ......................................................................................................................... 41
Completion of First Frame Reception (FCS Error) ................................................................................. 42
Start of Second Frame Reception ........................................................................................................... 43
Completion of Second Frame Reception ................................................................................................ 44
External Memory Configuration Example ............................................................................................... 45
3-1 Initialization Steps for µPD72103A and External Memory ..................................................................... 47
3-2 Transmission Timing ................................................................................................................................ 49
3-3 Reception Timing (External Clock Mode) ............................................................................................... 51
3-4 Reception Timing (DPLL Mode) .............................................................................................................. 52
3-5 Idle Reception Count ............................................................................................................................... 54
6-1 µPD72103A System Configuration Example (Local Memory Type) .................................................... 113
6-2 µPD72103A System Configuration Example (Main Memory Type) ..................................................... 114
6-3 Two-wire Interface Example .................................................................................................................. 115
6-4 Connection Example with ISDN LSI (connection with SIFC [µPD98201]) .......................................... 115
– iii –







D72103A equivalent, schematic
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CHAPTER 1 GENERAL
Pin No.
80-pin 68-pin
QFP QFJ
Pin name
I/O Active
level
Function
24 12 B/W
(Byte/Word)
I L/H During bus master mode, this indicates the data bus used to access
external memory.
When B/W = 0: byte unit (8 bits)
When B/W = 1: word unit (16 bits)
The status of the B/W pin should be fixed after power-on.
When accessing in word units, the low-order bits in the data bus are
the data contents of even-number addresses.
25 13 TEST
(Text)
I – When using this pin, it should be pulled up to high level.
26 14 CLK
(Clock)
I – System clock input
Input a 1-MHz to 16-MHz clock to this pin. Note
27 15 GND
– – Ground pins
Make sure that there are several ground pins.
28 16 GND
– – Ground pins
Make sure that there are several ground pins.
29 – NC
– – Leave this pin unconnected.
(No Connection)
30 and 31 17 and 18 A0 and A1
I/O – Bi-directional During bus master mode: (output)
*
3-state
Indicates the low-order two bits of the memory
address line
access address.
During bus slave mode: (input)
These pins are used to input addresses during
I/O access to the µPD72103A by an external
host.
32 to 39 19 to 26 A2 to A9
O – During bus master mode:
* Outputs memory addresses from 2 bits to 15 bits.
During bus slave mode:
Changes to high impedance.
40 – NC
– – Leave this pin unconnected.
(No Connection)
41 – NC
– – Leave this pin unconnected.
(No Connection)
42 to 47 27 to 32 A10 to A15
O – See “A2 to A9” above.
*
48 and 49 33 and 34 A16D8 and A17D9 I/O – These pins are for the bi-directional 3-state/data bus.
* They are multiplex pins for high-order 8 bits starting from bits 16 to
23 of an address and for high-order 8 bits starting from bits 8 to 15
of the data.
50 35 NC
– – Leave this pin unconnected.
(No Connection)
51 – NC
– – Leave this pin unconnected.
(No Connection)
52 to 54 36 to 38 A18D10 to A20D12 I/O – See “A16D8 and A17D9” above.
*
Note See the caution points described in “3.4.8 Cautions regarding overrun errors”.
Remark “*” indicates 3-state.
7










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